Reference : Heterogeneous Integration and Fabrication of III-V MOS Devices in a 200mm Processing Env...
Scientific congresses and symposiums : Paper published in a book
Engineering, computing & technology : Electrical & electronics engineering
http://hdl.handle.net/2268/77722
Heterogeneous Integration and Fabrication of III-V MOS Devices in a 200mm Processing Environment
English
Waldron, Niamh mailto [IMEC > > > >]
Nguyen, Ngoc Duy mailto [Université de Liège - ULg > Département de physique > Physique des solides, interfaces et nanostructures >]
Lin, Dennis [IMEC > > > >]
Brammertz, Guy [IMEC > > > >]
Vincent, Benjamin [IMEC > > > >]
Firrincieli, Andrea [Katholieke Universiteit Leuven - KUL and IMEC > Department of Metallurgy and Materials Engineering > > >]
Winderickx, Gillis [IMEC > > > >]
Sioncke, Sonja [IMEC > > > >]
De Jaeger, Brice [IMEC > > > >]
Wang, Gang [IMEC > > > >]
Mitard, Jérôme [IMEC > > > >]
Wang, Wei-E [IMEC > > > >]
Heyns, Marc [Katholieke Universiteit Leuven - KUL and IMEC > Department of Metallurgy and Materials Engineering > > >]
Caymax, Matty [IMEC > > > >]
Meuris, Marc [IMEC > > > >]
Absil, Philippe [IMEC > > > >]
Hoffman, Thomas [IMEC > > > >]
2011
ECS
219th ECS Meeting
ECS
ECS Meeting Abstracts MA2011-01
No
Yes
International
2151-2043
Pennington
USA
219th ECS Meeting
1-6/5/2011
ECS
Montreal
Canada
[en] III-V ; CMOS ; Device fabrication
[en] As CMOS continues to scales to more advanced nodes, new higher mobility channel materials will have to be introduced as an alternative to Si in order to meet power and performance requirements [1]. III-V and Ge materials have emerged as an attractive option for nMOS and pMOS respectively. However, from an economical and technological standpoint it must be possible to implement III-V devices in a Si CMOS fabrication environment to leverage the advantages of both large scale wafers and state-of-the-art Si equipment. The integration challenges of introducing III-V into a Si line include safety risk assessments from toxic materials, maintenance of tools after processing III-V, cross-contamination from high- temperature and wet etch steps, and modifying standard recipes where III-V is exposed on the surface. In this work we demonstrate the feasibility of processing III-V virtual substrates in a Si line following a CMOS based approach that seeks to minimize any potential cross- contamination from the III-V.
Researchers ; Professionals
http://hdl.handle.net/2268/77722

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