Reference : Substrates and Gate Dielectrics: the Materials Issue for sub-22 nm CMOS Scaling
Scientific congresses and symposiums : Unpublished conference
Physical, chemical, mathematical & earth Sciences : Physics
Substrates and Gate Dielectrics: the Materials Issue for sub-22 nm CMOS Scaling
Caymax, Matty mailto [IMEC > > > >]
Bellenger, Florence [Katholieke Universiteit Leuven - KUL and IMEC > Department of Electrical Engineering > > >]
Brammertz, Guy [IMEC > > > >]
Dekoster, Johan [IMEC > > > >]
Delabie, Annelies [IMEC > > > >]
Loo, Roger [IMEC > > > >]
Merckling, Clement [IMEC > > > >]
Nguyen, Ngoc Duy mailto [Université de Liège - ULg > Département de physique > Physique des solides, interfaces et nanostructures >]
Nijns, Laura [IMEC > > > >]
Sioncke, Sonja [IMEC > > > >]
Vincent, Benjamin [IMEC > > > >]
Wang, Gang [IMEC > > > >]
Vandervorst, Wilfried [Katholieke Universiteit Leuven - KUL and IMEC > Instituut voor Kern-en Stralingsfysica > > >]
Heyns, Marc [Katholieke Universiteit Leuven - KUL and IMEC > Department of Metallurgy and Materials Engineering > > >]
MRS Spring 2010 Meeting
Materials Research Society
San Francisco
[en] CMOS scaling ; sub-22 nm CMOS
[en] Performance scaling of CMOS technologies beyond the 22 nm node will depend on the successful introduction of high mobility materials such as germanium and compound semiconductors on silicon substrates, which is not straightforward due to important materials incompatibilities. These semiconductors moreover necessitate new gate dielectric materials as the well-proven recipes of “hafnium-based oxides” are not working for various reasons. The lack of a stable, high-quality native oxide for both semiconductors forces materials scientists and device engineers to focus more on the interface rather than on the dielectric material it self. A first part of this paper discusses problems related to the hetero-epitaxial growth of Ge and of III/V materials on Si. By applying a low-high temperature regime, smooth layers of Ge on Si can be obtained. Because of the lattice mismatch, these layers will relax by the formation of misfit dislocations at the interface, combined with threading arms that extend to the surface. The thickness of the layer determines the final density of threading defects, even in case of confined selective growth in windows in a dielectric hard mask, unless specific measures are taken. The polar nature of III/V’s brings about additional problems of anti-phase domain nucleation. This can be solved by providing extra steps on the starting surface in combination with a “pre-deposition” of arsenic. The combination of Ge and III/V selective epitaxy on patterned wafers allows growing confined layers with a low defect density and of high quality. Moreover, by using standard shallow trench isolation as mask, a very natural integration of these materials in standard Si manufacturing can be realized. The second part of this paper deals with the growth of dielectric materials and control of the resulting interfaces. In contrast to the case of Si, both Ge and III/V surfaces are heavily prone to problems with pinning of the surface Fermi level (FLP), which prohibits an efficient control of the channel by varying gate voltages. In the case of Ge, the problem can be solved by decoupling the gate dielectric from the Ge surface by means of an ultra-thin, strained Si epi-layer, after which the well-known gate stack approaches with ALD-grown metal oxides from the Si world can be used. An alternative, promising solution is passivation with thermally grown GeO2 followed by ALD high-k, although this process requires much more care than its Si counterpart. Gate dielectrics on III/V, finally, are probably an even bigger challenge. Apart from the Ga2O+GaGdOx passivation on GaAs, no real solutions of the FLP problem are known. We will discuss the use of sulfur (from thermal treatments with H2S or in the liquid phase with (NH4)2S) in combination with ALD or MBD-grown high-k layers on both GaAs and InGaAs. This will be compared to alternative approaches based on an epitaxially grown interfacial passivation layer of Ge in combination with MBD-grown Al2O3.
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