Reference : Selective epitaxial growth of III-V semiconductor on large-area Si substrate for advance...
Scientific congresses and symposiums : Unpublished conference
Engineering, computing & technology : Electrical & electronics engineering
http://hdl.handle.net/2268/69191
Selective epitaxial growth of III-V semiconductor on large-area Si substrate for advanced logic CMOS technologies
English
Nguyen, Ngoc Duy mailto [IMEC > > > >]
Brammertz, Guy [IMEC > > > >]
Wang, Gang [IMEC > > > >]
Lismont, Kevin [IMEC > > > >]
Dekoster, Johan [IMEC > > > > > >]
Degroote, Stefan [IMEC > > > >]
Leys, Maarten [IMEC > > > >]
Nollet, Vincent [IMEC > > > >]
Caymax, Matty [IMEC > > > >]
Buttita, Francesco [AIXTRON AG > > > >]
Féron, Olivier [AIXTRON AG > > > >]
O'Neil, Barry [AIXTRON AG > > > > > >]
Lindner, Johannes [AIXTRON AG > > > > > >]
Schulte, Frank [AIXTRON AG > > > > > >]
Schineller, Bernd [AIXTRON AG > > > > > >]
Heuken, Michael [AIXTRON AG > > > > > >]
2010
No
International
E-MRS Spring Meeting, 2010; Symposium H : Post-Si CMOS electronic devices: the role of Ge and III-V materials
7-11/6/2010
E-MRS
Strasbourg
France
[en] III-V compound ; Selective epitaxial growth ; CMOS
[en] The continued downscaling of the metal-oxide semiconductor (MOS) transistor for sub-22 nm logic circuits with boosted performance will require the introduction of new channel materials with carrier mobility higher than that of Si, such as Ge for pMOS. The use of III-V compounds for nMOS devices poses however additional challenges related to the hetero-epitaxial growth of a polar semiconductor on a non-polar surface. Furthermore, these high-mobility materials have to be fabricated on large-area Si substrates, in the perspective of application in a standard low-cost very-large-scale integration scheme. In this work, we report on the successful growth of GaAs on 200 mm Si wafers by means of metal-organic vapor deposition using a modified Crius Close-Coupled Showerhead system from AIXTRON AG. We used Si (100) wafers with off-axis orientation (6° miscut towards <111>) in order to avoid the formation of anti-phase domains which lead to Ga-Ga and As-As bonds at their boundaries that have strong detrimental effects on the electrical conduction. In our approach, based on Ge virtual substrates with low threading dislocation (TD) density, the lattice mismatch between Si and GaAs is accommodated and, thus, no additional TD is introduced in the deposited III-V film. Our results show that smooth GaAs layers can be epitaxially grown on large-area Si substrates with high wafer-scale thickness uniformity. The excellent quality of the deposited GaAs was confirmed by photoluminescence and electron microscopy. Our process also demonstrates very high selectivity on patterned wafers with SiO2 mask and enabled the fabrication of capacitor structures using an integration process flow very similar to standard high volume Si manufacturing lines. The capacitance-voltage characteristics were similar to the ones obtained on a bulk GaAs substrate, and showed extremely tight within-wafer and wafer-to-wafer distributions as is standard to Si manufacturing.
Researchers ; Professionals
http://hdl.handle.net/2268/69191

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