Reference : A 35nm diameter vertical silicon nanowire short-gate tunnelFET
Scientific congresses and symposiums : Unpublished conference
Engineering, computing & technology : Electrical & electronics engineering
http://hdl.handle.net/2268/69119
A 35nm diameter vertical silicon nanowire short-gate tunnelFET
English
Vandooren, A. [IMEC > > > > > >]
Rooyackers, R. [IMEC > > > > > >]
Leonelli, D. [IMEC > > > > > >]
Iacopi, F. [IMEC > > > > > >]
De Gendt, S. [IMEC > > > > > >]
Verhulst, A. [IMEC > > > > > >]
Heyns, M. [Katholieke Universiteit Leuven - KUL and IMEC > Department of Metallurgy and Materials Engineering > > > >]
Kunnen, E. [IMEC > > > > > >]
Nguyen, Ngoc Duy mailto [IMEC > > > >]
Demand, M. [IMEC > > > > > >]
Ong, P. [IMEC > > > > > >]
Lee, W. [IMEC > > > > > >]
Moonens, J. [IMEC > > > > > >]
Richard, O. [IMEC > > > > > >]
Vandenberghe, W. [IMEC > > > > > >]
Groeseneken, G. [Katholieke Universiteit Leuven - KUL and IMEC > Department of Metallurgy and Materials Engineering > > > >]
2009
No
No
International
Nanotechnology Workshop
13-14/6/2009
Kyoto
Japan
[en] Nanowire ; Tunnel FET ; Vertical device
[en] A top-down integration scheme for silicon vertical nanowire (NW) tunnel field-effect transistors (TFETs) with a 35nm nanowire dimension and using state-of-the-art metal gate and high-k gate dielectric is demonstrated. Using the short-gate concept [1], the ambipolar behavior of the TFET is successfully suppressed. The measured TFET performance is not yet beyond that of the MOSFET, most likely due to the use of silicon that has a large bandgap and the use of ion implantation for the formation of the tunnel junction which results in a low junction abruptness. To boost the device performance, a low thermal budget processing could be used on etched nanowires in a substrate with epitaxial grown junction, in order to increase the abruptness of the tunnel junction.
Researchers ; Professionals
http://hdl.handle.net/2268/69119

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