Impact of traps on the electrical characteristics of GeSn/Ge diodes

Germanium-tin alloys are currently receiving a lot of attention as materials for high performance MOSFET devices. Much interest is focused on the direct band gap for Sn concentrations above 8-10% and the achievement of high mobility values, which can be further increased by the strain due to the lattice mismatch with Ge or Si. GeSn is therefore expected to play a key role in the development of either source and drain stressors for Ge p-MOSFETs or for GeSn channel MOSFETs. However, despite recent tremendous progress in the growth of such materials, the impact of defects at the interface between Ge and GeSn has not been completely characterized. As the processing of diodes contains many of the steps necessary to the fabrication of MOSFET devices, we have investigated the effect of traps on the electrical characteristics of p-GeSn/n-Ge diodes, made from GeSn layers grown by CVD on Ge and in-situ doped with Boron. Using temperature-dependent current-voltage (I-V) and capacitance-
voltage (C-V) measurements, we have calculated the ideality factor of the diodes, the activation energy of the reverse saturation current and the carrier concentration of the Ge substrate. In this work, based on the comparison with results obtained from numerical simulations, we discuss these characteristics in view of assessing the extent to which electronic trap states in these heterostructures affect their electrical properties.