Reference : Integration of InGaAs Channel n-MOS Devices on 200mm Si Wafers Using the Aspect-Ratio...
Scientific journals : Article
Physical, chemical, mathematical & earth Sciences : Physics
http://hdl.handle.net/2268/127833
Integration of InGaAs Channel n-MOS Devices on 200mm Si Wafers Using the Aspect-Ratio-Trapping Technique
English
Waldron, Niamh [IMEC > > > >]
Wang, Gang [MEMC > > > >]
Nguyen, Ngoc Duy mailto [Université de Liège - ULg > Département de physique > Physique des solides, interfaces et nanostructures >]
Orzali, Tommaso [IMEC > > > >]
Merckling, Clément [IMEC > > > >]
Brammertz, Guy [IMEC > > > >]
Ong, Patrick [IMEC > > > >]
Winderickx, Gillis [IMEC > > > >]
Hellings, Geert [IMEC > > > >]
Eneman, Geert [IMEC > > > >]
Caymax, Matty [IMEC > > > >]
Meuris, Marc [IMEC > > > >]
Horiguchi, Naoto [IMEC > > > >]
Thean, Aaron [IMEC > > > >]
2012
ECS Transactions
The Electrochemical Society
45
115
Yes
International
1938-5862
1938-6737
Pennington
NJ
[en] III-V ; InGaAs ; MOS
[en] We report on the fabrication on InGaAs/InP implant free quantum well (IFQW) n-MOSFET devices on 200mm wafers in a Si CMOS processing environment. The starting virtual InP substrates were prepared by means of the aspect-ratio-trapping technique. Post CMP these substrate resulted in a planar substrate with a rms roughness of 0.32 nm. After channel and gate processing source drain regions were formed by the selective epitaxial growth of Si doped InGaAs. Contact to the source/drain regions was made by a standard W-plug/metal 1 process. The contact resistance was estimated to be on the order of 7x10-7 [ohm sign].cm2. Fully processed devices clearly showed gate modulation albeit on top of high levels of source to drain leakage. The source of this leakage was determined to be the result of the unintentional background doping of the InP buffer layer. Simulations show that the inclusion of the p-InAlAs between the InP and InGaAs can effectively suppress this leakage. This work is a significant step towards the integration of InGaAs based devices on a standard CMOS platform.
Researchers ; Professionals
http://hdl.handle.net/2268/127833
10.1149/1.3700460

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