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See detailImpedance Spectroscopy of GeSn-based Heterostructures
Baert, Bruno ULg; Nakatsuka, Osamu; Zaima, Shigeaki et al

in ECS Transactions (2013), 50(9), 481-490

In this work, we investigated the electrical characteristics of p-GeSn/p-Ge and p-GeSn/n-Ge structures obtained by simulation of the basic semiconductor equations. We developed a numerical formalism based ... [more ▼]

In this work, we investigated the electrical characteristics of p-GeSn/p-Ge and p-GeSn/n-Ge structures obtained by simulation of the basic semiconductor equations. We developed a numerical formalism based on a drift-diffusion model including a trap level and applied it to typical GeSn-based heterostructures by focusing on the electrical response under small-signal alternating current regime. The results demonstrate that our method provides an access to both microscopic and macroscopic properties, and thereon, to a physical interpretation of the electrical characteristics of GeSn-based structures by linking measurable quantities to micro-scale variations in the structures. [less ▲]

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See detailIntegration of InGaAs Channel n-MOS Devices on 200mm Si Wafers Using the Aspect-Ratio-Trapping Technique
Waldron, Niamh; Wang, Gang; Nguyen, Ngoc Duy ULg et al

in ECS Transactions (2012), 45

We report on the fabrication on InGaAs/InP implant free quantum well (IFQW) n-MOSFET devices on 200mm wafers in a Si CMOS processing environment. The starting virtual InP substrates were prepared by means ... [more ▼]

We report on the fabrication on InGaAs/InP implant free quantum well (IFQW) n-MOSFET devices on 200mm wafers in a Si CMOS processing environment. The starting virtual InP substrates were prepared by means of the aspect-ratio-trapping technique. Post CMP these substrate resulted in a planar substrate with a rms roughness of 0.32 nm. After channel and gate processing source drain regions were formed by the selective epitaxial growth of Si doped InGaAs. Contact to the source/drain regions was made by a standard W-plug/metal 1 process. The contact resistance was estimated to be on the order of 7x10-7 [ohm sign].cm2. Fully processed devices clearly showed gate modulation albeit on top of high levels of source to drain leakage. The source of this leakage was determined to be the result of the unintentional background doping of the InP buffer layer. Simulations show that the inclusion of the p-InAlAs between the InP and InGaAs can effectively suppress this leakage. This work is a significant step towards the integration of InGaAs based devices on a standard CMOS platform. [less ▲]

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See detailHeterogeneous Integration and Fabrication of III-V MOS Devices in a 200mm Processing Environment
Waldron, Niamh; Nguyen, Ngoc Duy ULg; Lin, Dennis et al

in ECS Transactions (2011), 35

We report on the fabrication of MOS capacitors on 200 mm virtual GaAs substrates using a Si CMOS processing environment. The fabricated capacitors were comparable to those processed on bulk GaAs material ... [more ▼]

We report on the fabrication of MOS capacitors on 200 mm virtual GaAs substrates using a Si CMOS processing environment. The fabricated capacitors were comparable to those processed on bulk GaAs material. Topside contact was made to the GaAs using a novel CMOS compatible self-aligned NiGe contact scheme resulting in a measured contact resistance of 0.26 [ohm sign].cm. Cross-contamination from various III-V substrates was investigated and it was found that by limiting the thermal budget to <= 300C cross-contamination from the outgassing of In, Ga and As could be eliminated. For wet processing the judicious choice of recipe and processing conditions resulted in no significant cross-contamination being detected as determined by TXRF monitoring. This achievement enables III-V device production using state-of-the-art Si processing equipment. [less ▲]

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See detailSelective epitaxial growth of InP in STI trenches on off-axis Si(001) substrates
Wang, Gang; Nguyen, Ngoc Duy ULg; Leys, Maarten et al

in ECS Transactions (2010), 27

We report high quality InP layers selectively grown in shallow trench isolation structures on 6 degree offcut Si (001) substrates capped with a thin Ge buffer layer. The Ge layer was used to reduce the ... [more ▼]

We report high quality InP layers selectively grown in shallow trench isolation structures on 6 degree offcut Si (001) substrates capped with a thin Ge buffer layer. The Ge layer was used to reduce the thermal budget for surface clean and double step formation. The atomic steps on the Ge surface were recovered after a bake at 680°C. Smooth nucleation layer was obtained at 420°C on the Ge surface. Baking the Ge surface in As ambient facilitates the InP nulceation and improves the InP crystalline quality. This improvement is attributed to the effective As adsorption on the Ge surface and the polar Ge:As surface prevents the islanding of InP seed layer. Stacking faults were found in the InP layers as a result of threading dislocation dissociation and high quality InP layers were obtained in trenches with aspect ratio greater than 2. [less ▲]

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See detailSelective epitaxial growth of III-V semiconductor heterostructures on Si substrates for logic applications
Nguyen, Ngoc Duy ULg; Wang, Gang; Brammertz, Guy et al

in ECS Transactions (2010), 33

We have deposited III-V alloys on 200 mm Si miscut wafers with an oxide pattern. The selective epitaxial growth (SEG) of GaAs in large windows defined by SiO2 lines on a thick strained-relaxed Ge buffer ... [more ▼]

We have deposited III-V alloys on 200 mm Si miscut wafers with an oxide pattern. The selective epitaxial growth (SEG) of GaAs in large windows defined by SiO2 lines on a thick strained-relaxed Ge buffer layer served as a test vehicle which allowed us to demonstrate the integration of a III-V material deposition process step in a Si manufacturing line using an industrial reactor. High quality GaAs layers with high wafer-scale thickness uniformity were achieved. In a subsequent step, SEG of InP was successfully performed on wafers with a 300 nm shallow trench isolation pattern. The seed layer morphology depended on the treatment of the Ge surface and on the growth temperature. The orientation of the trench with respect to the substrate miscut direction had an impact on the quality of the InP filling. Despite of the challenges, such an approach for the integration of III-V materials on Si substrates allowed us to obtain extended-defect-free epitaxial regions suitable for the fabrication of high-performance devices. [less ▲]

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See detailGrowth of III/V materials on large area silicon
Schineller, Bernd; Nguyen, Ngoc Duy ULg; Heuken, Michael

in ECS Transactions (2010), 28

Continuous miniaturization has been at the heart of advances in modern semiconductor electronics. However, further scalability has seen its limits for conventional CMOS technology due to short channel ... [more ▼]

Continuous miniaturization has been at the heart of advances in modern semiconductor electronics. However, further scalability has seen its limits for conventional CMOS technology due to short channel effects. To further increase the performance for the 32 and 22 nm nodes, channel engineering introducing III-V materials may be necessary. Hence, epitaxial growth and processing strategies have to be developed which combine the high complexity of an MOCVD growth chamber with the requirements of the silicon industry. [less ▲]

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See detailTentative determination of the acidity level in room temperature ionic liquids by electrochemical methods
Malherbe, Cédric ULg; Robert, Thierry ULg; Magna, Lionel et al

in ECS Transactions (2009), 16(49), 3

In our attempt to evaluate the acidity levels reached by acidified ionic liquids (BMImBF4, BMImNTf2 and BMImOTf + HOTf or HNTf2), the uncertainty on the pKas of the indicators needed for the Hammett ... [more ▼]

In our attempt to evaluate the acidity levels reached by acidified ionic liquids (BMImBF4, BMImNTf2 and BMImOTf + HOTf or HNTf2), the uncertainty on the pKas of the indicators needed for the Hammett spectrophotometric procedure was pointed out. As consequence another method is proposed, based on the H+/H2 couple potential measurement. In this purpose, if dynamic methods failed mainly for lack of sufficient reversibility, potentiometry with a hydrogen electrode gave meaningful results. The R0(H+) Strehlow function, could be calculated, using the Fc+-Fc couple as reference assumed as solvent independent. The obtained results show that i) the acidities are much higher than those in water; ii) the acidities measured by the hydrogen electrode are higher than those measured by the Hammett method; iii) the sequence of acidities for solutions of similar content of added acid is still BF4 > NTf2 > OTf as previously measured with the Hammett method. [less ▲]

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See detailStrained silicon on wafer level by wafer bonding: materials processing, strain measurements and strain relaxation
Reiche, M.; Moutanabbir, O.; Himcinschi, C. et al

in ECS Transactions (2008), 16

Different methods to introduce strain in thin silicon device layers are presented. Uniaxial strain is introduced in CMOS devices by process-induced stressors allowing the local generation of tensile or ... [more ▼]

Different methods to introduce strain in thin silicon device layers are presented. Uniaxial strain is introduced in CMOS devices by process-induced stressors allowing the local generation of tensile or compressive strain in the channel region of MOSFETs. Biaxial strain is introduced by growing thin silicon layer on SiGe buffer and transferring it to an oxidized silicon substrates. The latter forms strained silicon on insulator (SSOI) wafer characterized by tensile strain only. Future CMOS device technologies require the combination of the global strain of SSOI substrates with local stressors to increase the device performance. [less ▲]

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See detailVapor phase doping with N-type dopant into silicon by atmospheric pressure chemical vapor deposition
Takeuchi, Shotaro; Nguyen, Ngoc Duy ULg; Leys, Frederik et al

in ECS Transactions (2008), 16

Atomic layer doping of phosphorus (P) and arsenic (As) into Si was performed using the vapor phase doping (VPD) technique. For increasing deposition time and precursor gas flow rate, the P and As doses ... [more ▼]

Atomic layer doping of phosphorus (P) and arsenic (As) into Si was performed using the vapor phase doping (VPD) technique. For increasing deposition time and precursor gas flow rate, the P and As doses tend to saturate at about 0.8 and 1.0 monolayer of Si, respectively. Therefore, these processes are self-limited in both cases. When a Si cap layer is grown on the P-covered Si(001), high P concentration of 3.7 × 1020 cm-3 at the heterointerface in the Si- cap/P/Si-substrate layer stacks is achieved. Due to As desorption and segregation toward the Si surface during the temperature ramp up and during the Si-cap growth, the As concentration at the heterointerface in the Si-cap/As/Si-substrate layer stacks was lower compared to the P case. These results allowed us to evaluate the feasibility of the VPD process to fabricate precisely controlled doping profiles. [less ▲]

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See detailAbout the Acidity Level in Room Temperature Ionic Liquids
Robert, Thierry ULg; Olivier-Bourbigou, Hélène; Magna, Lionel et al

in ECS Transactions (2007), 3(35), 71

The Brønsted acidity level was evaluated for ionic liquids to which a strong acid has been added. The evaluation method is based on the determination of the Hammett acidity functions H0, using UV-Visible ... [more ▼]

The Brønsted acidity level was evaluated for ionic liquids to which a strong acid has been added. The evaluation method is based on the determination of the Hammett acidity functions H0, using UV-Visible spectroscopy. The acidity of protons is mainly determined by their solvation state and consequently, the properties of protons depend on both the nature of the solvent and the nature and concentration of the acid. In practice, it was found that, for the investigated ionic liquids, the cation as well as the added acid nature does not play a dominant role, whereas changing the anion nature may lead to very different acidities. Indeed, for a similar content of added acid, the measured acidity levels are in the order: PF6- > BF4- > NTf2- > OTf-. The problems of the influence of impurities on the final acidity and of the weakly dissociating character of the ionic liquid are addressed. [less ▲]

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See detailIn-line characterization of heterojunction bipolar transistor base layers by high-resolution x-ray diffraction
Nguyen, Ngoc Duy ULg; Loo, R.; Hikavyy, A. et al

in ECS Transactions (2007), 10

The suitability of high-resolution X-ray diffraction (HRXRD) as an in-line measurement tool for the characterization of heterojunction bipolar transistor SiGe base layers and Si cap layers was ... [more ▼]

The suitability of high-resolution X-ray diffraction (HRXRD) as an in-line measurement tool for the characterization of heterojunction bipolar transistor SiGe base layers and Si cap layers was investigated. We showed that despite of polycrystalline Si on the mask material of patterned wafers, HRXRD measurements performed on an array of small windows yield results which are comparable to those that were obtained on a window which is larger than the size of the source beam, regarding the thickness and the Ge content of the SiGe layers. The possibility to extract layer parameters for active device windows of different sizes was therefore demonstrated. The suitability of HRXRD for in-line measurement of the Si cap thickness was also assessed and the sensitivity of this technique for determining the substitutional boron concentration in SiGe was studied. The detection limit in the monitoring of the active dopant concentration was about 2.7 × 1019 cm-3. [less ▲]

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See detailStrained silicon-on-insulator - Fabrication and characterization
Reiche, M.; Himcinschi, C.; Gösele, U. et al

in ECS Transactions (2007), 6

SSOI substrates were successfully fabricated using He+ ion implantation and annealing to relax thin (< 500nm) SiGe buffer layers, bonding and layer transfer processes to realize strained-Si layers onto ... [more ▼]

SSOI substrates were successfully fabricated using He+ ion implantation and annealing to relax thin (< 500nm) SiGe buffer layers, bonding and layer transfer processes to realize strained-Si layers onto oxide layers. The reduced thickness of the SiGe buffer possess numerous advantages such as reduced process costs for epitaxy and for reclaim of the handle wafer if the layer splitting is initiated in the SiGe/Si interface. The electron mobilities in the fabricated SSOI layers were measured using transistors with different gate lengths. An electron mobility of ~530 cm2 /Vs was extracted, being much higher than in non-strained SOI substrates. Furthermore, an 80% drive current (IDSAT) improvement has been measured for long channel devices. [less ▲]

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