Bandgap Measurement by Spectroscopic Ellipsometry for Strained Ge1-xSnx

Conference (2013, June 04)

Composition and Thickness Dependence of GeSn Growth by Chemical Vapor Deposition

Conference (2013, June 04)

Study of interface trap density in a GeSn MOS structure by numerical simulation of the electrical characteristics

Conference (2013, May)

The semiconducting alloy germanium tin (GeSn) is expected to play an important role in the development of high mobility channel materials for next generation CMOS and optoelectronic devices. The two most ... [more ▼]

The semiconducting alloy germanium tin (GeSn) is expected to play an important role in the development of high mobility channel materials for next generation CMOS and optoelectronic devices. The two most interesting features of this material, which is compatible with mainstream Si technology, are its tunable direct band-gap and the possibility to induce strain due to the lattice mismatch with Ge and Si, thereby increasing the holes and electrons mobilities. It has been shown that the interface trap density can be under- or overestimated in Ge-channel MOSFETs when applying conventional measurement techniques such as the conductance method. As this effect is common in low band-gap materials, we expect that it also occurs for GeSn. Following our previous work on metal/GeSn/Ge structures, we have therefore applied our home-built numerical simulation software to a metal/oxide/GeSn MOS structure in order to investigate the result of the presence of such interface states. We discuss possible effects of the interface trap density, interface trap energy and temperature on the electrical characteristics. Successive simulations of both the steady-state and ac small-signal regimes give access to measurable quantities such as the admittance spectrum and the C-V curves. A physical interpretation can be attributed to their variations and an overall comparison can be made with results obtained from equivalent electrical circuit analysis. [less ▲]

Long term stability of TiO2 templated multilayer films used as high efficiency photoelectrode in liquid DSSCs

Poster (2013, March)

To our knowledge, the stability results reported in the literature only concern cells made from classical doctor-bladed or screen-printed nanoparticles films. This study focuses on the comparison of the ... [more ▼]

To our knowledge, the stability results reported in the literature only concern cells made from classical doctor-bladed or screen-printed nanoparticles films. This study focuses on the comparison of the long-term stability of these cells with DSSCs working with templated mesoporous films. Indeed, the increased surface area of templated films could lead to a faster degradation of the resulting cells. In accordance with IEC:1646:1996 standard tests, light soaking test at 45°C has been applied to determine the cells stability under prolonged illumination. Moreover, thermal stress in the dark has been applied. Unfortunately, due to the sealing material heat resistance, thermal stress test was only performed at 45°C. [less ▲]

Impedance Spectroscopy of GeSn-based Heterostructures

in ECS Transactions (2013), 50(9), 481-490

In this work, we investigated the electrical characteristics of p-GeSn/p-Ge and p-GeSn/n-Ge structures obtained by simulation of the basic semiconductor equations. We developed a numerical formalism based ... [more ▼]

In this work, we investigated the electrical characteristics of p-GeSn/p-Ge and p-GeSn/n-Ge structures obtained by simulation of the basic semiconductor equations. We developed a numerical formalism based on a drift-diffusion model including a trap level and applied it to typical GeSn-based heterostructures by focusing on the electrical response under small-signal alternating current regime. The results demonstrate that our method provides an access to both microscopic and macroscopic properties, and thereon, to a physical interpretation of the electrical characteristics of GeSn-based structures by linking measurable quantities to micro-scale variations in the structures. [less ▲]

Numerical Simulation of the Electrical Characteristics of GeSn/Ge Semiconducting Heterostructures

Poster (2012, June)

Proceedings of the 7th International Conference on Si Epitaxy and Heterostructures (ICSI-7)

Book published by Elsevier (2012)

Integration of InGaAs Channel n-MOS Devices on 200mm Si Wafers Using the Aspect-Ratio-Trapping Technique

in ECS Transactions (2012), 45

We report on the fabrication on InGaAs/InP implant free quantum well (IFQW) n-MOSFET devices on 200mm wafers in a Si CMOS processing environment. The starting virtual InP substrates were prepared by means ... [more ▼]

We report on the fabrication on InGaAs/InP implant free quantum well (IFQW) n-MOSFET devices on 200mm wafers in a Si CMOS processing environment. The starting virtual InP substrates were prepared by means of the aspect-ratio-trapping technique. Post CMP these substrate resulted in a planar substrate with a rms roughness of 0.32 nm. After channel and gate processing source drain regions were formed by the selective epitaxial growth of Si doped InGaAs. Contact to the source/drain regions was made by a standard W-plug/metal 1 process. The contact resistance was estimated to be on the order of 7x10-7 [ohm sign].cm2. Fully processed devices clearly showed gate modulation albeit on top of high levels of source to drain leakage. The source of this leakage was determined to be the result of the unintentional background doping of the InP buffer layer. Simulations show that the inclusion of the p-InAlAs between the InP and InGaAs can effectively suppress this leakage. This work is a significant step towards the integration of InGaAs based devices on a standard CMOS platform. [less ▲]

Integration of III-V on Si for High-Mobility CMOS

Conference (2012)

Arsenic-doped Ge-spiked monoemitter SiGe:C heterojunction bipolar transistors by low-temperature trisilane-based chemical vapor deposition

in Thin Solid Films (2012), 520

In this work we optimized the Ge-spiked monoemitter for the SiGe:C heterojunction bipolar transistor by using low-temperature trisilane based chemical vapor deposition to meet the requirements of high ... [more ▼]

In this work we optimized the Ge-spiked monoemitter for the SiGe:C heterojunction bipolar transistor by using low-temperature trisilane based chemical vapor deposition to meet the requirements of high growth rate and high electrically-active doping levels of arsenic. The resultant devices show improvement of open-base breakdown voltage and no degradation of cutoff frequency with incorporation of a Ge spike in the monoemitter. [less ▲]