References of "Vincent, Benjamin"
     in
Bookmark and Share    
Peer Reviewed
See detailTheoretical and experimental investigation of the GeSn bandgap
Shimura, Yosuke; Wang, Wei; Gencarelli, Federica et al

Conference (2013, September)

Detailed reference viewed: 36 (0 ULg)
Peer Reviewed
See detailBandgap Measurement by Spectroscopic Ellipsometry for Strained Ge1-xSnx
Shimura, Yosuke; Wang, Wei; Nieddu, Thomas ULg et al

Conference (2013, June 04)

Detailed reference viewed: 105 (3 ULg)
Peer Reviewed
See detailComposition and Thickness Dependence of GeSn Growth by Chemical Vapor Deposition
Wang, Wei; Shimura, Yosuke; Nieddu, Thomas ULg et al

Conference (2013, June 04)

Detailed reference viewed: 68 (1 ULg)
Full Text
Peer Reviewed
See detailHeterogeneous Integration and Fabrication of III-V MOS Devices in a 200mm Processing Environment
Waldron, Niamh; Nguyen, Ngoc Duy ULg; Lin, Dennis et al

in ECS Transactions (2011), 35

We report on the fabrication of MOS capacitors on 200 mm virtual GaAs substrates using a Si CMOS processing environment. The fabricated capacitors were comparable to those processed on bulk GaAs material ... [more ▼]

We report on the fabrication of MOS capacitors on 200 mm virtual GaAs substrates using a Si CMOS processing environment. The fabricated capacitors were comparable to those processed on bulk GaAs material. Topside contact was made to the GaAs using a novel CMOS compatible self-aligned NiGe contact scheme resulting in a measured contact resistance of 0.26 [ohm sign].cm. Cross-contamination from various III-V substrates was investigated and it was found that by limiting the thermal budget to <= 300C cross-contamination from the outgassing of In, Ga and As could be eliminated. For wet processing the judicious choice of recipe and processing conditions resulted in no significant cross-contamination being detected as determined by TXRF monitoring. This achievement enables III-V device production using state-of-the-art Si processing equipment. [less ▲]

Detailed reference viewed: 56 (5 ULg)
Full Text
See detailHeterogeneous Integration and Fabrication of III-V MOS Devices in a 200mm Processing Environment
Waldron, Niamh; Nguyen, Ngoc Duy ULg; Lin, Dennis et al

in 219th ECS Meeting (2011)

As CMOS continues to scales to more advanced nodes, new higher mobility channel materials will have to be introduced as an alternative to Si in order to meet power and performance requirements [1]. III-V ... [more ▼]

As CMOS continues to scales to more advanced nodes, new higher mobility channel materials will have to be introduced as an alternative to Si in order to meet power and performance requirements [1]. III-V and Ge materials have emerged as an attractive option for nMOS and pMOS respectively. However, from an economical and technological standpoint it must be possible to implement III-V devices in a Si CMOS fabrication environment to leverage the advantages of both large scale wafers and state-of-the-art Si equipment. The integration challenges of introducing III-V into a Si line include safety risk assessments from toxic materials, maintenance of tools after processing III-V, cross-contamination from high- temperature and wet etch steps, and modifying standard recipes where III-V is exposed on the surface. In this work we demonstrate the feasibility of processing III-V virtual substrates in a Si line following a CMOS based approach that seeks to minimize any potential cross- contamination from the III-V. [less ▲]

Detailed reference viewed: 148 (3 ULg)
See detailEpitaxial Si, SiGe and Ge for high-performance devices
Loo, Roger; Hikavyy, Andriy; Vincent, Benjamin et al

Conference (2010, September 23)

Detailed reference viewed: 78 (5 ULg)
See detailSubstrates and Gate Dielectrics: the Materials Issue for sub-22 nm CMOS Scaling
Caymax, Matty; Bellenger, Florence; Brammertz, Guy et al

Conference (2010, April 08)

Performance scaling of CMOS technologies beyond the 22 nm node will depend on the successful introduction of high mobility materials such as germanium and compound semiconductors on silicon substrates ... [more ▼]

Performance scaling of CMOS technologies beyond the 22 nm node will depend on the successful introduction of high mobility materials such as germanium and compound semiconductors on silicon substrates, which is not straightforward due to important materials incompatibilities. These semiconductors moreover necessitate new gate dielectric materials as the well-proven recipes of “hafnium-based oxides” are not working for various reasons. The lack of a stable, high-quality native oxide for both semiconductors forces materials scientists and device engineers to focus more on the interface rather than on the dielectric material it self. A first part of this paper discusses problems related to the hetero-epitaxial growth of Ge and of III/V materials on Si. By applying a low-high temperature regime, smooth layers of Ge on Si can be obtained. Because of the lattice mismatch, these layers will relax by the formation of misfit dislocations at the interface, combined with threading arms that extend to the surface. The thickness of the layer determines the final density of threading defects, even in case of confined selective growth in windows in a dielectric hard mask, unless specific measures are taken. The polar nature of III/V’s brings about additional problems of anti-phase domain nucleation. This can be solved by providing extra steps on the starting surface in combination with a “pre-deposition” of arsenic. The combination of Ge and III/V selective epitaxy on patterned wafers allows growing confined layers with a low defect density and of high quality. Moreover, by using standard shallow trench isolation as mask, a very natural integration of these materials in standard Si manufacturing can be realized. The second part of this paper deals with the growth of dielectric materials and control of the resulting interfaces. In contrast to the case of Si, both Ge and III/V surfaces are heavily prone to problems with pinning of the surface Fermi level (FLP), which prohibits an efficient control of the channel by varying gate voltages. In the case of Ge, the problem can be solved by decoupling the gate dielectric from the Ge surface by means of an ultra-thin, strained Si epi-layer, after which the well-known gate stack approaches with ALD-grown metal oxides from the Si world can be used. An alternative, promising solution is passivation with thermally grown GeO2 followed by ALD high-k, although this process requires much more care than its Si counterpart. Gate dielectrics on III/V, finally, are probably an even bigger challenge. Apart from the Ga2O+GaGdOx passivation on GaAs, no real solutions of the FLP problem are known. We will discuss the use of sulfur (from thermal treatments with H2S or in the liquid phase with (NH4)2S) in combination with ALD or MBD-grown high-k layers on both GaAs and InGaAs. This will be compared to alternative approaches based on an epitaxially grown interfacial passivation layer of Ge in combination with MBD-grown Al2O3. [less ▲]

Detailed reference viewed: 90 (6 ULg)
Full Text
Peer Reviewed
See detailIII-V Devices for Advanced CMOS
Waldron, Niamh; Nguyen, Ngoc Duy ULg; Lin, Dennis et al

in 217th ECS Meeting (2010)

Detailed reference viewed: 31 (2 ULg)