References of "Vandervorst, Wilfried"
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See detailComposition and Thickness Dependence of GeSn Growth by Chemical Vapor Deposition
Wang, Wei; Shimura, Yosuke; Nieddu, Thomas ULg et al

Conference (2013, June 04)

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See detailN-type and p-type ultra shallow junctions by atomic layer epitaxy and laser anneal
Nguyen, Ngoc Duy ULg; Souriau, Laurent; Shimizu, Yasuo et al

Conference (2011)

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See detailSubstrates and Gate Dielectrics: the Materials Issue for sub-22 nm CMOS Scaling
Caymax, Matty; Bellenger, Florence; Brammertz, Guy et al

Conference (2010, April 08)

Performance scaling of CMOS technologies beyond the 22 nm node will depend on the successful introduction of high mobility materials such as germanium and compound semiconductors on silicon substrates ... [more ▼]

Performance scaling of CMOS technologies beyond the 22 nm node will depend on the successful introduction of high mobility materials such as germanium and compound semiconductors on silicon substrates, which is not straightforward due to important materials incompatibilities. These semiconductors moreover necessitate new gate dielectric materials as the well-proven recipes of “hafnium-based oxides” are not working for various reasons. The lack of a stable, high-quality native oxide for both semiconductors forces materials scientists and device engineers to focus more on the interface rather than on the dielectric material it self. A first part of this paper discusses problems related to the hetero-epitaxial growth of Ge and of III/V materials on Si. By applying a low-high temperature regime, smooth layers of Ge on Si can be obtained. Because of the lattice mismatch, these layers will relax by the formation of misfit dislocations at the interface, combined with threading arms that extend to the surface. The thickness of the layer determines the final density of threading defects, even in case of confined selective growth in windows in a dielectric hard mask, unless specific measures are taken. The polar nature of III/V’s brings about additional problems of anti-phase domain nucleation. This can be solved by providing extra steps on the starting surface in combination with a “pre-deposition” of arsenic. The combination of Ge and III/V selective epitaxy on patterned wafers allows growing confined layers with a low defect density and of high quality. Moreover, by using standard shallow trench isolation as mask, a very natural integration of these materials in standard Si manufacturing can be realized. The second part of this paper deals with the growth of dielectric materials and control of the resulting interfaces. In contrast to the case of Si, both Ge and III/V surfaces are heavily prone to problems with pinning of the surface Fermi level (FLP), which prohibits an efficient control of the channel by varying gate voltages. In the case of Ge, the problem can be solved by decoupling the gate dielectric from the Ge surface by means of an ultra-thin, strained Si epi-layer, after which the well-known gate stack approaches with ALD-grown metal oxides from the Si world can be used. An alternative, promising solution is passivation with thermally grown GeO2 followed by ALD high-k, although this process requires much more care than its Si counterpart. Gate dielectrics on III/V, finally, are probably an even bigger challenge. Apart from the Ga2O+GaGdOx passivation on GaAs, no real solutions of the FLP problem are known. We will discuss the use of sulfur (from thermal treatments with H2S or in the liquid phase with (NH4)2S) in combination with ALD or MBD-grown high-k layers on both GaAs and InGaAs. This will be compared to alternative approaches based on an epitaxially grown interfacial passivation layer of Ge in combination with MBD-grown Al2O3. [less ▲]

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See detailNon-destructive extraction of junction depths of active doping profiles from photomodulated optical reflectance offset curves
Bogdanowicz, Janusz; Dortu, Fabian; Clarysse, Trudo et al

in Journal of Vacuum Science & Technology : Part B (2010), 28(1), 11

The ITRS Roadmap highlights the electrical characterization of the source and drain extension regions as a key challenge for future complimentary-metal-oxide-semiconductor technology. Presently, an ... [more ▼]

The ITRS Roadmap highlights the electrical characterization of the source and drain extension regions as a key challenge for future complimentary-metal-oxide-semiconductor technology. Presently, an accurate determination of the depth of ultrashallow junctions can routinely only be performed by time-consuming and destructive techniques such as secondary ion mass spectrometry (SIMS). In this work, the authors propose to use the fast and nondestructive photomodulated optical reflectance (PMOR) technique , as implemented in the Therma-Probe\textregistered (TP) dopant metrology system, for these purposes. PMOR is a pump-probe technique based on the measurement of the pump-induced modulated change in probe reflectance, i.e., the so-called (photo) modulated reflectance. In this article, the authors demonstrate that the absolute junction depths of boxlike active dopant structures can be extracted in a very simple and straightforward way from the TP offset curves, which represent the behavior of the modulated reflectance as a function of the pump-probe beam spacing. Although the procedure is based on the insights into the physical behavior of the offset curves, no modeling is involved in the actual extraction process itself. The extracted junction depths are in good correlation with the corresponding junction depths as measured by means of SIMS. The technique has a subnanometer depth sensitivity for depths ranging from 10 to 35 nm with the present Therma-Probe\textregistered 630XP system. The extension of the proposed procedure to the general ultrashallow profiles is also explored and discussed [less ▲]

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See detailVapor phase doping for ultra shallow junction formation in advanced Si CMOS devices
Shimizu, Yasuo; Nguyen, Ngoc Duy ULg; Jiang, Sijia et al

Poster (2010)

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See detailUse of p- and n-type vapor phase doping and sub-melt laser anneal for extension junctions in sub-32 nm CMOS technology
Nguyen, Ngoc Duy ULg; Rosseel, Erik; Takeuchi, Shotaro et al

in Thin Solid Films (2009), 518(6), 48

We evaluated the combination of vapor phase doping and sub-melt laser anneal as a novel doping strategy for the fabrication of source and drain extension junctions in sub-32 nm CMOS technology, aiming at ... [more ▼]

We evaluated the combination of vapor phase doping and sub-melt laser anneal as a novel doping strategy for the fabrication of source and drain extension junctions in sub-32 nm CMOS technology, aiming at both planar and non-planar device applications. High quality ultra shallow junctions with abrupt profiles in Si substrates were demonstrated on 300 mm Si substrates. The excellent results obtained for the sheet resistance and the junction depth with boron allowed us to fulfill the requirements for the 32 nm as well as for the 22 nm technology nodes in the PMOS case by choosing appropriate laser anneal conditions. For instance, using 3 laser scans at 1300 $\,^ rc$C, we measured an active dopant concentration of about 2.1 × 1020 cm− 3 and a junction depth of 12 nm. With arsenic for NMOS, ultra shallow junctions were achieved as well. However, as also seen for other junction fabrication schemes, low dopant activation level and active dose (in the range of 1--4 × 1013 cm− 2) were observed although dopant concentration versus depth profiles indicate that the dopant atoms were properly driven into the substrate during the anneal step. The electrical deactivation of a large part of the in-diffused dopants was responsible for the high sheet resistance values. [less ▲]

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See detailVapor phase doping and sub-melt laser anneal for the fabrication of Si-based ultra-shallow junctions in sub-32 nm CMOS technology
Nguyen, Ngoc Duy ULg; Rosseel, Erik; Takeuchi, Shotaro et al

in International Semiconductor Device Research Symposium, 2009 (2009)

The authors demonstrated that the combination of VPD and LA enables the fabrication of high quality, defect-free USJs with abrupt dopant profile. The results for PMOS with B-VPD are very promising for the ... [more ▼]

The authors demonstrated that the combination of VPD and LA enables the fabrication of high quality, defect-free USJs with abrupt dopant profile. The results for PMOS with B-VPD are very promising for the 32 nm and the 22 nm technology nodes. In the case of NMOS, As-VPD and LA enable the fabrication of an USJ but the electrical deactivation of a large part of the in-diffused dopants is responsible for the high sheet resistance values. [less ▲]

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See detailDepth resolution and surface transients in crystalline Silicon at ultra low energies
Goossens, Jozefien; Berghmans, Bart; Franquet, Alexis et al

Poster (2009)

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See detailVapor phase doping and sub-melt laser anneal for ultra-shallow extension junctions in sub-32 nm CMOS technology
Nguyen, Ngoc Duy ULg; Rosseel, Erik; Takeuchi, Shotaro et al

in Chiussi, S.; Alpuim, P.; Murota, J. (Eds.) et al SiNEP 2009. 1st International Workshop on Si based nano-electronics and -photonics (2009)

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See detailVapor phase doping: an atomic layer deposition approach to n-type doping in classical chemical vapor deposition epitaxy
Takeuchi, Shotaro; Nguyen, Ngoc Duy ULg; Leys, Frederik et al

Conference (2008)

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See detailConformal doping of FINFET's : a fabrication and metrology challenge
Vandervorst, Wilfried; Eyben, Pierre; Mody, Jay et al

Conference (2008)

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See detailVapor phase doping with N-type dopant into silicon by atmospheric pressure chemical vapor deposition
Takeuchi, Shotaro; Nguyen, Ngoc Duy ULg; Leys, Frederik et al

in ECS Transactions (2008), 16

Atomic layer doping of phosphorus (P) and arsenic (As) into Si was performed using the vapor phase doping (VPD) technique. For increasing deposition time and precursor gas flow rate, the P and As doses ... [more ▼]

Atomic layer doping of phosphorus (P) and arsenic (As) into Si was performed using the vapor phase doping (VPD) technique. For increasing deposition time and precursor gas flow rate, the P and As doses tend to saturate at about 0.8 and 1.0 monolayer of Si, respectively. Therefore, these processes are self-limited in both cases. When a Si cap layer is grown on the P-covered Si(001), high P concentration of 3.7 × 1020 cm-3 at the heterointerface in the Si- cap/P/Si-substrate layer stacks is achieved. Due to As desorption and segregation toward the Si surface during the temperature ramp up and during the Si-cap growth, the As concentration at the heterointerface in the Si-cap/As/Si-substrate layer stacks was lower compared to the P case. These results allowed us to evaluate the feasibility of the VPD process to fabricate precisely controlled doping profiles. [less ▲]

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See detailConformal ultra shallow junctions by vapor phase doping with boron
Nguyen, Ngoc Duy ULg; Leys, Frederik; Takeuchi, Shotaro et al

Poster (2008)

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See detailAtomic layer doping of phosphorus and arsenic: experimental and atomistic modeling
Takeuchi, Shotaro; Yang, Lijun; Nguyen, Ngoc Duy ULg et al

Poster (2008)

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See detailVapor phase doping with N-type dopant into silicon by atmospheric pressure chemical vapor deposition
Takeuchi, Shotaro; Nguyen, Ngoc Duy ULg; Leys, Frederik et al

in 214th ECS Meeting, 2008 (2008)

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