References of "Richard, Olivier"
     in
Bookmark and Share    
Full Text
Peer Reviewed
See detailGrowth of high quality InP layers in STI trenches on miscut Si (001) substrates
Wang, Gang; Leys, Maarten; Nguyen, Ngoc Duy ULg et al

in Journal of Crystal Growth (2011), 315

In this work, we report the selective area epitaxial growth of high quality InP in shallow trench isolation (STI) structures on Si (0 0 1) substrates 6° miscut toward (1 1 1) using a thin Ge buffer layer ... [more ▼]

In this work, we report the selective area epitaxial growth of high quality InP in shallow trench isolation (STI) structures on Si (0 0 1) substrates 6° miscut toward (1 1 1) using a thin Ge buffer layer. We studied the impact of growth rates and steric hindrance effects on the nano-twin formation at the STI side walls. It was found that a too high growth rate induces more nano-twins in the layer and results in InP crystal distortion. The STI side wall tapering angle and the substrate miscut angle induced streric hindrance between the InP facets and the STI side walls also contribute to defect formation. In the [-1 1 0] orientated trenches, when the STI side wall tapering angle is larger than 10°, crystal distortion was observed while the substrate miscut angle has no significant impact on the InP defect formation. In the [-1 1 0] trenches, both the increased STI tapering angle and the substrate miscut angle induce high density of defects. With a small STI tapering angle and a thin Ge layer, we obtained extended defect free InP in the top region of the [1 1 0] trenches with aspect ratio larger than 2. [less ▲]

Detailed reference viewed: 57 (6 ULg)
Full Text
Peer Reviewed
See detailSelective Area Growth of InP in Shallow-Trench-Isolated Structures on Off-Axis Si(001) Substrates
Wang, Gang; Leys, Maarten; Nguyen, Ngoc Duy ULg et al

in Journal of the Electrochemical Society (2010), 157(11), 1023

In this paper, we report a comprehensive investigation of InP selective growth in shallow trench isolation (STI) structures on Si(001) substrates 6° off-cut toward (111). Extended defect-free InP layers ... [more ▼]

In this paper, we report a comprehensive investigation of InP selective growth in shallow trench isolation (STI) structures on Si(001) substrates 6° off-cut toward (111). Extended defect-free InP layers were obtained in the top region of 100 nm wide trenches. A thin Ge epitaxial layer was used as an intermediate buffer layer between the Si substrate and the InP layer. A Ge buffer was used to reduce the thermal budget for surface clean and to promote double-step formation on the surfaces. Baking the Ge surface in an As ambient improved the InP surface morphology and crystalline quality. InP showed highly selective growth in trenches without nucleation on SiO2. However, strong loading effects were observed at all growth pressures, which induced variation in local growth rates. We found trench orientation dependence of facet and stacking fault formation. More stacking faults and nanotwins originated from the STI sidewalls in (110) trenches. High quality InP layers were obtained in the top of the trenches along (110). The stacking faults generated by the dissociation of threading dislocations are trapped at the bottom of the trenches with an aspect ratio greater than 2. [less ▲]

Detailed reference viewed: 83 (8 ULg)
Full Text
Peer Reviewed
See detailSelective epitaxial growth of InP in STI trenches on off-axis Si(001) substrates
Wang, Gang; Nguyen, Ngoc Duy ULg; Leys, Maarten et al

in ECS Transactions (2010), 27

We report high quality InP layers selectively grown in shallow trench isolation structures on 6 degree offcut Si (001) substrates capped with a thin Ge buffer layer. The Ge layer was used to reduce the ... [more ▼]

We report high quality InP layers selectively grown in shallow trench isolation structures on 6 degree offcut Si (001) substrates capped with a thin Ge buffer layer. The Ge layer was used to reduce the thermal budget for surface clean and double step formation. The atomic steps on the Ge surface were recovered after a bake at 680°C. Smooth nucleation layer was obtained at 420°C on the Ge surface. Baking the Ge surface in As ambient facilitates the InP nulceation and improves the InP crystalline quality. This improvement is attributed to the effective As adsorption on the Ge surface and the polar Ge:As surface prevents the islanding of InP seed layer. Stacking faults were found in the InP layers as a result of threading dislocation dissociation and high quality InP layers were obtained in trenches with aspect ratio greater than 2. [less ▲]

Detailed reference viewed: 57 (4 ULg)
Full Text
Peer Reviewed
See detailUse of p- and n-type vapor phase doping and sub-melt laser anneal for extension junctions in sub-32 nm CMOS technology
Nguyen, Ngoc Duy ULg; Rosseel, Erik; Takeuchi, Shotaro et al

in Thin Solid Films (2009), 518(6), 48

We evaluated the combination of vapor phase doping and sub-melt laser anneal as a novel doping strategy for the fabrication of source and drain extension junctions in sub-32 nm CMOS technology, aiming at ... [more ▼]

We evaluated the combination of vapor phase doping and sub-melt laser anneal as a novel doping strategy for the fabrication of source and drain extension junctions in sub-32 nm CMOS technology, aiming at both planar and non-planar device applications. High quality ultra shallow junctions with abrupt profiles in Si substrates were demonstrated on 300 mm Si substrates. The excellent results obtained for the sheet resistance and the junction depth with boron allowed us to fulfill the requirements for the 32 nm as well as for the 22 nm technology nodes in the PMOS case by choosing appropriate laser anneal conditions. For instance, using 3 laser scans at 1300 $\,^ rc$C, we measured an active dopant concentration of about 2.1 × 1020 cm− 3 and a junction depth of 12 nm. With arsenic for NMOS, ultra shallow junctions were achieved as well. However, as also seen for other junction fabrication schemes, low dopant activation level and active dose (in the range of 1--4 × 1013 cm− 2) were observed although dopant concentration versus depth profiles indicate that the dopant atoms were properly driven into the substrate during the anneal step. The electrical deactivation of a large part of the in-diffused dopants was responsible for the high sheet resistance values. [less ▲]

Detailed reference viewed: 47 (4 ULg)
Peer Reviewed
See detailDepth resolution and surface transients in crystalline Silicon at ultra low energies
Goossens, Jozefien; Berghmans, Bart; Franquet, Alexis et al

Poster (2009)

Detailed reference viewed: 21 (0 ULg)