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See detailIntegration of InGaAs Channel n-MOS Devices on 200mm Si Wafers Using the Aspect-Ratio-Trapping Technique
Waldron, Niamh; Wang, Gang; Nguyen, Ngoc Duy ULg et al

in ECS Transactions (2012), 45

We report on the fabrication on InGaAs/InP implant free quantum well (IFQW) n-MOSFET devices on 200mm wafers in a Si CMOS processing environment. The starting virtual InP substrates were prepared by means ... [more ▼]

We report on the fabrication on InGaAs/InP implant free quantum well (IFQW) n-MOSFET devices on 200mm wafers in a Si CMOS processing environment. The starting virtual InP substrates were prepared by means of the aspect-ratio-trapping technique. Post CMP these substrate resulted in a planar substrate with a rms roughness of 0.32 nm. After channel and gate processing source drain regions were formed by the selective epitaxial growth of Si doped InGaAs. Contact to the source/drain regions was made by a standard W-plug/metal 1 process. The contact resistance was estimated to be on the order of 7x10-7 [ohm sign].cm2. Fully processed devices clearly showed gate modulation albeit on top of high levels of source to drain leakage. The source of this leakage was determined to be the result of the unintentional background doping of the InP buffer layer. Simulations show that the inclusion of the p-InAlAs between the InP and InGaAs can effectively suppress this leakage. This work is a significant step towards the integration of InGaAs based devices on a standard CMOS platform. [less ▲]

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See detailIntegration of III-V on Si for High-Mobility CMOS
Waldron, Niamh; Wang, Gang; Nguyen, Ngoc Duy ULg et al

Conference (2012)

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See detailIntegration of InGaAs Channel n-MOS Devices on 200mm Si Wafers Using the Aspect-Ratio-Trapping Technique
Waldron, Niamh; Wang, Gang; Nguyen, Ngoc Duy ULg et al

in 221st ECS Meeting (2012)

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See detailHeterogeneous Integration and Fabrication of III-V MOS Devices in a 200mm Processing Environment
Waldron, Niamh; Nguyen, Ngoc Duy ULg; Lin, Dennis et al

in ECS Transactions (2011), 35

We report on the fabrication of MOS capacitors on 200 mm virtual GaAs substrates using a Si CMOS processing environment. The fabricated capacitors were comparable to those processed on bulk GaAs material ... [more ▼]

We report on the fabrication of MOS capacitors on 200 mm virtual GaAs substrates using a Si CMOS processing environment. The fabricated capacitors were comparable to those processed on bulk GaAs material. Topside contact was made to the GaAs using a novel CMOS compatible self-aligned NiGe contact scheme resulting in a measured contact resistance of 0.26 [ohm sign].cm. Cross-contamination from various III-V substrates was investigated and it was found that by limiting the thermal budget to <= 300C cross-contamination from the outgassing of In, Ga and As could be eliminated. For wet processing the judicious choice of recipe and processing conditions resulted in no significant cross-contamination being detected as determined by TXRF monitoring. This achievement enables III-V device production using state-of-the-art Si processing equipment. [less ▲]

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See detailHeterogeneous Integration and Fabrication of III-V MOS Devices in a 200mm Processing Environment
Waldron, Niamh; Nguyen, Ngoc Duy ULg; Lin, Dennis et al

in 219th ECS Meeting (2011)

As CMOS continues to scales to more advanced nodes, new higher mobility channel materials will have to be introduced as an alternative to Si in order to meet power and performance requirements [1]. III-V ... [more ▼]

As CMOS continues to scales to more advanced nodes, new higher mobility channel materials will have to be introduced as an alternative to Si in order to meet power and performance requirements [1]. III-V and Ge materials have emerged as an attractive option for nMOS and pMOS respectively. However, from an economical and technological standpoint it must be possible to implement III-V devices in a Si CMOS fabrication environment to leverage the advantages of both large scale wafers and state-of-the-art Si equipment. The integration challenges of introducing III-V into a Si line include safety risk assessments from toxic materials, maintenance of tools after processing III-V, cross-contamination from high- temperature and wet etch steps, and modifying standard recipes where III-V is exposed on the surface. In this work we demonstrate the feasibility of processing III-V virtual substrates in a Si line following a CMOS based approach that seeks to minimize any potential cross- contamination from the III-V. [less ▲]

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See detailSelective Area Growth of InP in Shallow-Trench-Isolated Structures on Off-Axis Si(001) Substrates
Wang, Gang; Leys, Maarten; Nguyen, Ngoc Duy ULg et al

in Journal of the Electrochemical Society (2010), 157(11), 1023

In this paper, we report a comprehensive investigation of InP selective growth in shallow trench isolation (STI) structures on Si(001) substrates 6° off-cut toward (111). Extended defect-free InP layers ... [more ▼]

In this paper, we report a comprehensive investigation of InP selective growth in shallow trench isolation (STI) structures on Si(001) substrates 6° off-cut toward (111). Extended defect-free InP layers were obtained in the top region of 100 nm wide trenches. A thin Ge epitaxial layer was used as an intermediate buffer layer between the Si substrate and the InP layer. A Ge buffer was used to reduce the thermal budget for surface clean and to promote double-step formation on the surfaces. Baking the Ge surface in an As ambient improved the InP surface morphology and crystalline quality. InP showed highly selective growth in trenches without nucleation on SiO2. However, strong loading effects were observed at all growth pressures, which induced variation in local growth rates. We found trench orientation dependence of facet and stacking fault formation. More stacking faults and nanotwins originated from the STI sidewalls in (110) trenches. High quality InP layers were obtained in the top of the trenches along (110). The stacking faults generated by the dissociation of threading dislocations are trapped at the bottom of the trenches with an aspect ratio greater than 2. [less ▲]

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See detailSelective epitaxial growth of III-V semiconductor heterostructures on Si substrates for logic applications
Nguyen, Ngoc Duy ULg; Wang, Gang; Brammertz, Guy et al

in ECS Transactions (2010), 33

We have deposited III-V alloys on 200 mm Si miscut wafers with an oxide pattern. The selective epitaxial growth (SEG) of GaAs in large windows defined by SiO2 lines on a thick strained-relaxed Ge buffer ... [more ▼]

We have deposited III-V alloys on 200 mm Si miscut wafers with an oxide pattern. The selective epitaxial growth (SEG) of GaAs in large windows defined by SiO2 lines on a thick strained-relaxed Ge buffer layer served as a test vehicle which allowed us to demonstrate the integration of a III-V material deposition process step in a Si manufacturing line using an industrial reactor. High quality GaAs layers with high wafer-scale thickness uniformity were achieved. In a subsequent step, SEG of InP was successfully performed on wafers with a 300 nm shallow trench isolation pattern. The seed layer morphology depended on the treatment of the Ge surface and on the growth temperature. The orientation of the trench with respect to the substrate miscut direction had an impact on the quality of the InP filling. Despite of the challenges, such an approach for the integration of III-V materials on Si substrates allowed us to obtain extended-defect-free epitaxial regions suitable for the fabrication of high-performance devices. [less ▲]

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See detailSelective epitaxial growth of InP in STI trenches on off-axis Si(001) substrates
Wang, Gang; Nguyen, Ngoc Duy ULg; Leys, Maarten et al

in ECS Transactions (2010), 27

We report high quality InP layers selectively grown in shallow trench isolation structures on 6 degree offcut Si (001) substrates capped with a thin Ge buffer layer. The Ge layer was used to reduce the ... [more ▼]

We report high quality InP layers selectively grown in shallow trench isolation structures on 6 degree offcut Si (001) substrates capped with a thin Ge buffer layer. The Ge layer was used to reduce the thermal budget for surface clean and double step formation. The atomic steps on the Ge surface were recovered after a bake at 680°C. Smooth nucleation layer was obtained at 420°C on the Ge surface. Baking the Ge surface in As ambient facilitates the InP nulceation and improves the InP crystalline quality. This improvement is attributed to the effective As adsorption on the Ge surface and the polar Ge:As surface prevents the islanding of InP seed layer. Stacking faults were found in the InP layers as a result of threading dislocation dissociation and high quality InP layers were obtained in trenches with aspect ratio greater than 2. [less ▲]

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See detailIII-V Devices for Advanced CMOS
Waldron, Niamh; Nguyen, Ngoc Duy ULg; Lin, Dennis et al

in 217th ECS Meeting (2010)

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See detailSelective epitaxial growth of III-V semiconductor heterostructures on Si substrates for logic applications
Nguyen, Ngoc Duy ULg; Wang, Gang; Waldron, Niamh et al

in 218th ECS Meeting, 2010 (2010)

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