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See detailRelaxation of strained pseudomorphic SixGe1-x layers on He-implanted Si/δ-Si:C/Si(100) substrates
Buca, D.; Minamisawa, R. A.; Trinkaus, H. et al

in Applied Physics Letters (2009), 95

In this letter we present a method to increase the efficiency of SiGe layer relaxation by He+ ion implantation and annealing. Preferential nucleation of He platelets along a 􏰀-impurity layer grown in the ... [more ▼]

In this letter we present a method to increase the efficiency of SiGe layer relaxation by He+ ion implantation and annealing. Preferential nucleation of He platelets along a 􏰀-impurity layer grown in the Si substrate below the SiGe layer results in planar localization and homogenization of dislocation loop sources inducing a more uniform distribution of misfit dislocations. We demonstrate this for a thin Si:C layer grown by reduced pressure chemical vapor deposition. The optimization of the conditions for efficient relaxation and layer quality is studied with respect to the position of the Si:C layer and the process parameters. Relaxation degrees up to 85% are obtained for Si0.77Ge0.23 layers. [less ▲]

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See detailStrained silicon on wafer level by wafer bonding: materials processing, strain measurements and strain relaxation
Reiche, M.; Moutanabbir, O.; Himcinschi, C. et al

in ECS Transactions (2008), 16

Different methods to introduce strain in thin silicon device layers are presented. Uniaxial strain is introduced in CMOS devices by process-induced stressors allowing the local generation of tensile or ... [more ▼]

Different methods to introduce strain in thin silicon device layers are presented. Uniaxial strain is introduced in CMOS devices by process-induced stressors allowing the local generation of tensile or compressive strain in the channel region of MOSFETs. Biaxial strain is introduced by growing thin silicon layer on SiGe buffer and transferring it to an oxidized silicon substrates. The latter forms strained silicon on insulator (SSOI) wafer characterized by tensile strain only. Future CMOS device technologies require the combination of the global strain of SSOI substrates with local stressors to increase the device performance. [less ▲]

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See detailImprovement of He ion induced SiGe layer relaxation by a thin Si:C layer
Buca, D.; Trinkaus, H.; Holländer, B. et al

Conference (2008)

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See detailStrained silicon on wafer level by wafer bonding: materials processing, strain measurements and strain relaxation
Reiche, M.; Moutanabbir, O.; Himcinschi, C. et al

Conference (2008)

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See detailFabrication, characterization, and modeling of strained SOI MOSFETs with very large effective mobility
Driussi, F.; Esseni, D.; Selmi, L. et al

in IEEE (Ed.) 37th European Solid State Device Research Conference (ESSDERC) (2007)

Strained silicon on insulators (sSOI) wafers with a supercritical thickness of 58 nm were produced using thin strain relaxed SiGe buffer layers, wafer bonding, selective etch back and epitaxial overgrowth ... [more ▼]

Strained silicon on insulators (sSOI) wafers with a supercritical thickness of 58 nm were produced using thin strain relaxed SiGe buffer layers, wafer bonding, selective etch back and epitaxial overgrowth. Raman spectroscopy revealed an homogeneous strain of 0.63 plusmn 0.03 % in the strained Si layer. Long channel n-type SOI-MOSFETs showed very large electron mobilities up to 1200 cm2/Vs in the strained Si devices. These values are more than two times larger than those of reference SOI n-MOSFETs. Mobility simulations with state of the art scattering models are then used to interpret the experiments. [less ▲]

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See detailStrained silicon-on-insulator - Fabrication and characterization
Reiche, M.; Himcinschi, C.; Gösele, U. et al

in 211th ECS Meeting, 2007 (2007)

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See detailIn-line characterization of heterojunction bipolar transistor base layers by high-resolution x-ray diffraction
Nguyen, Ngoc Duy ULg; Loo, R.; Hikavyy, A. et al

in ECS Transactions (2007), 10

The suitability of high-resolution X-ray diffraction (HRXRD) as an in-line measurement tool for the characterization of heterojunction bipolar transistor SiGe base layers and Si cap layers was ... [more ▼]

The suitability of high-resolution X-ray diffraction (HRXRD) as an in-line measurement tool for the characterization of heterojunction bipolar transistor SiGe base layers and Si cap layers was investigated. We showed that despite of polycrystalline Si on the mask material of patterned wafers, HRXRD measurements performed on an array of small windows yield results which are comparable to those that were obtained on a window which is larger than the size of the source beam, regarding the thickness and the Ge content of the SiGe layers. The possibility to extract layer parameters for active device windows of different sizes was therefore demonstrated. The suitability of HRXRD for in-line measurement of the Si cap thickness was also assessed and the sensitivity of this technique for determining the substitutional boron concentration in SiGe was studied. The detection limit in the monitoring of the active dopant concentration was about 2.7 × 1019 cm-3. [less ▲]

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See detailStrained silicon-on-insulator - Fabrication and characterization
Reiche, M.; Himcinschi, C.; Gösele, U. et al

in ECS Transactions (2007), 6

SSOI substrates were successfully fabricated using He+ ion implantation and annealing to relax thin (< 500nm) SiGe buffer layers, bonding and layer transfer processes to realize strained-Si layers onto ... [more ▼]

SSOI substrates were successfully fabricated using He+ ion implantation and annealing to relax thin (< 500nm) SiGe buffer layers, bonding and layer transfer processes to realize strained-Si layers onto oxide layers. The reduced thickness of the SiGe buffer possess numerous advantages such as reduced process costs for epitaxy and for reclaim of the handle wafer if the layer splitting is initiated in the SiGe/Si interface. The electron mobilities in the fabricated SSOI layers were measured using transistors with different gate lengths. An electron mobility of ~530 cm2 /Vs was extracted, being much higher than in non-strained SOI substrates. Furthermore, an 80% drive current (IDSAT) improvement has been measured for long channel devices. [less ▲]

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See detailLarge current enhancement in n-MOSFETs with strained Si on insulator
Mantl, S.; Buca, D.; Zhao, Q. et al

in International Semiconductor Device Research Symposium, 2007 (2007)

As scaling of the critical transistor dimensions below 65 nm has been slowed down, the implementation of novel materials, especially high mobility channel materials is most attractive to boost the ... [more ▼]

As scaling of the critical transistor dimensions below 65 nm has been slowed down, the implementation of novel materials, especially high mobility channel materials is most attractive to boost the transistor performance. Applying strain to silicon has become a successful route. The electron mobility can be enhanced by biaxial strain introduced into Si by epitaxial growth of Si on a strain relaxed SiGe layer or by so called process induced methods applied directly on transistor level. The combination of strained Si and SOI is particularly promising due to the combination of the enhanced mobilities and the inherent advantages of SOI. First long channel n-MOSFETs with gate lengths of 5 to 50 mum and a 6.6 nm thick SiO2 gate dielectric were fabricated. For comparison, devices on unstrained SOI were made. The transfer characteristics of a fully depleted sSOI-MOSFET with a gate length of 5 mum and a gate width of 20 mum indicating an inverse sub-threshold slope of 75mV/dec. [less ▲]

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See detailStrained Si-on-insulator for advanced CMOS devices
Mantl, S.; Buca, D.; Zhao, Q. et al

Poster (2007)

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See detailEnhancement of the relaxation of SiGe layers by He ion implantation using a delta-Si:C layer
Buca, D.; Goryll, M.; Holländer, B. et al

Conference (2007)

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