References of "Dekoster, Johan"
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See detailEpitaxial Si, SiGe and Ge for high-performance devices
Loo, Roger; Hikavyy, Andriy; Vincent, Benjamin et al

Conference (2010, September 23)

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See detailSelective Area Growth of InP in Shallow-Trench-Isolated Structures on Off-Axis Si(001) Substrates
Wang, Gang; Leys, Maarten; Nguyen, Ngoc Duy ULg et al

in Journal of the Electrochemical Society (2010), 157(11), 1023

In this paper, we report a comprehensive investigation of InP selective growth in shallow trench isolation (STI) structures on Si(001) substrates 6° off-cut toward (111). Extended defect-free InP layers ... [more ▼]

In this paper, we report a comprehensive investigation of InP selective growth in shallow trench isolation (STI) structures on Si(001) substrates 6° off-cut toward (111). Extended defect-free InP layers were obtained in the top region of 100 nm wide trenches. A thin Ge epitaxial layer was used as an intermediate buffer layer between the Si substrate and the InP layer. A Ge buffer was used to reduce the thermal budget for surface clean and to promote double-step formation on the surfaces. Baking the Ge surface in an As ambient improved the InP surface morphology and crystalline quality. InP showed highly selective growth in trenches without nucleation on SiO2. However, strong loading effects were observed at all growth pressures, which induced variation in local growth rates. We found trench orientation dependence of facet and stacking fault formation. More stacking faults and nanotwins originated from the STI sidewalls in (110) trenches. High quality InP layers were obtained in the top of the trenches along (110). The stacking faults generated by the dissociation of threading dislocations are trapped at the bottom of the trenches with an aspect ratio greater than 2. [less ▲]

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See detailSubstrates and Gate Dielectrics: the Materials Issue for sub-22 nm CMOS Scaling
Caymax, Matty; Bellenger, Florence; Brammertz, Guy et al

Conference (2010, April 08)

Performance scaling of CMOS technologies beyond the 22 nm node will depend on the successful introduction of high mobility materials such as germanium and compound semiconductors on silicon substrates ... [more ▼]

Performance scaling of CMOS technologies beyond the 22 nm node will depend on the successful introduction of high mobility materials such as germanium and compound semiconductors on silicon substrates, which is not straightforward due to important materials incompatibilities. These semiconductors moreover necessitate new gate dielectric materials as the well-proven recipes of “hafnium-based oxides” are not working for various reasons. The lack of a stable, high-quality native oxide for both semiconductors forces materials scientists and device engineers to focus more on the interface rather than on the dielectric material it self. A first part of this paper discusses problems related to the hetero-epitaxial growth of Ge and of III/V materials on Si. By applying a low-high temperature regime, smooth layers of Ge on Si can be obtained. Because of the lattice mismatch, these layers will relax by the formation of misfit dislocations at the interface, combined with threading arms that extend to the surface. The thickness of the layer determines the final density of threading defects, even in case of confined selective growth in windows in a dielectric hard mask, unless specific measures are taken. The polar nature of III/V’s brings about additional problems of anti-phase domain nucleation. This can be solved by providing extra steps on the starting surface in combination with a “pre-deposition” of arsenic. The combination of Ge and III/V selective epitaxy on patterned wafers allows growing confined layers with a low defect density and of high quality. Moreover, by using standard shallow trench isolation as mask, a very natural integration of these materials in standard Si manufacturing can be realized. The second part of this paper deals with the growth of dielectric materials and control of the resulting interfaces. In contrast to the case of Si, both Ge and III/V surfaces are heavily prone to problems with pinning of the surface Fermi level (FLP), which prohibits an efficient control of the channel by varying gate voltages. In the case of Ge, the problem can be solved by decoupling the gate dielectric from the Ge surface by means of an ultra-thin, strained Si epi-layer, after which the well-known gate stack approaches with ALD-grown metal oxides from the Si world can be used. An alternative, promising solution is passivation with thermally grown GeO2 followed by ALD high-k, although this process requires much more care than its Si counterpart. Gate dielectrics on III/V, finally, are probably an even bigger challenge. Apart from the Ga2O+GaGdOx passivation on GaAs, no real solutions of the FLP problem are known. We will discuss the use of sulfur (from thermal treatments with H2S or in the liquid phase with (NH4)2S) in combination with ALD or MBD-grown high-k layers on both GaAs and InGaAs. This will be compared to alternative approaches based on an epitaxially grown interfacial passivation layer of Ge in combination with MBD-grown Al2O3. [less ▲]

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See detailSelective epitaxial growth of III-V semiconductor heterostructures on Si substrates for logic applications
Nguyen, Ngoc Duy ULg; Wang, Gang; Brammertz, Guy et al

in ECS Transactions (2010), 33

We have deposited III-V alloys on 200 mm Si miscut wafers with an oxide pattern. The selective epitaxial growth (SEG) of GaAs in large windows defined by SiO2 lines on a thick strained-relaxed Ge buffer ... [more ▼]

We have deposited III-V alloys on 200 mm Si miscut wafers with an oxide pattern. The selective epitaxial growth (SEG) of GaAs in large windows defined by SiO2 lines on a thick strained-relaxed Ge buffer layer served as a test vehicle which allowed us to demonstrate the integration of a III-V material deposition process step in a Si manufacturing line using an industrial reactor. High quality GaAs layers with high wafer-scale thickness uniformity were achieved. In a subsequent step, SEG of InP was successfully performed on wafers with a 300 nm shallow trench isolation pattern. The seed layer morphology depended on the treatment of the Ge surface and on the growth temperature. The orientation of the trench with respect to the substrate miscut direction had an impact on the quality of the InP filling. Despite of the challenges, such an approach for the integration of III-V materials on Si substrates allowed us to obtain extended-defect-free epitaxial regions suitable for the fabrication of high-performance devices. [less ▲]

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See detailSelective epitaxial growth of III-V semiconductor on large-area Si substrate for advanced logic CMOS technologies
Nguyen, Ngoc Duy ULg; Brammertz, Guy; Wang, Gang et al

Conference (2010)

The continued downscaling of the metal-oxide semiconductor (MOS) transistor for sub-22 nm logic circuits with boosted performance will require the introduction of new channel materials with carrier ... [more ▼]

The continued downscaling of the metal-oxide semiconductor (MOS) transistor for sub-22 nm logic circuits with boosted performance will require the introduction of new channel materials with carrier mobility higher than that of Si, such as Ge for pMOS. The use of III-V compounds for nMOS devices poses however additional challenges related to the hetero-epitaxial growth of a polar semiconductor on a non-polar surface. Furthermore, these high-mobility materials have to be fabricated on large-area Si substrates, in the perspective of application in a standard low-cost very-large-scale integration scheme. In this work, we report on the successful growth of GaAs on 200 mm Si wafers by means of metal-organic vapor deposition using a modified Crius Close-Coupled Showerhead system from AIXTRON AG. We used Si (100) wafers with off-axis orientation (6° miscut towards <111>) in order to avoid the formation of anti-phase domains which lead to Ga-Ga and As-As bonds at their boundaries that have strong detrimental effects on the electrical conduction. In our approach, based on Ge virtual substrates with low threading dislocation (TD) density, the lattice mismatch between Si and GaAs is accommodated and, thus, no additional TD is introduced in the deposited III-V film. Our results show that smooth GaAs layers can be epitaxially grown on large-area Si substrates with high wafer-scale thickness uniformity. The excellent quality of the deposited GaAs was confirmed by photoluminescence and electron microscopy. Our process also demonstrates very high selectivity on patterned wafers with SiO2 mask and enabled the fabrication of capacitor structures using an integration process flow very similar to standard high volume Si manufacturing lines. The capacitance-voltage characteristics were similar to the ones obtained on a bulk GaAs substrate, and showed extremely tight within-wafer and wafer-to-wafer distributions as is standard to Si manufacturing. [less ▲]

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See detailSelective epitaxial growth of III-V semiconductor heterostructures on Si substrates for logic applications
Nguyen, Ngoc Duy ULg; Wang, Gang; Waldron, Niamh et al

in 218th ECS Meeting, 2010 (2010)

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