References of "Caymax, Matty"
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See detailProceedings of the 7th International Conference on Si Epitaxy and Heterostructures (ICSI-7)
Hartmann, Jean-Michel; Loo, Roger; Nguyen, Ngoc Duy ULg et al

Book published by Elsevier (2012)

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See detailIntegration of InGaAs Channel n-MOS Devices on 200mm Si Wafers Using the Aspect-Ratio-Trapping Technique
Waldron, Niamh; Wang, Gang; Nguyen, Ngoc Duy ULg et al

in ECS Transactions (2012), 45

We report on the fabrication on InGaAs/InP implant free quantum well (IFQW) n-MOSFET devices on 200mm wafers in a Si CMOS processing environment. The starting virtual InP substrates were prepared by means ... [more ▼]

We report on the fabrication on InGaAs/InP implant free quantum well (IFQW) n-MOSFET devices on 200mm wafers in a Si CMOS processing environment. The starting virtual InP substrates were prepared by means of the aspect-ratio-trapping technique. Post CMP these substrate resulted in a planar substrate with a rms roughness of 0.32 nm. After channel and gate processing source drain regions were formed by the selective epitaxial growth of Si doped InGaAs. Contact to the source/drain regions was made by a standard W-plug/metal 1 process. The contact resistance was estimated to be on the order of 7x10-7 [ohm sign].cm2. Fully processed devices clearly showed gate modulation albeit on top of high levels of source to drain leakage. The source of this leakage was determined to be the result of the unintentional background doping of the InP buffer layer. Simulations show that the inclusion of the p-InAlAs between the InP and InGaAs can effectively suppress this leakage. This work is a significant step towards the integration of InGaAs based devices on a standard CMOS platform. [less ▲]

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See detailIntegration of III-V on Si for High-Mobility CMOS
Waldron, Niamh; Wang, Gang; Nguyen, Ngoc Duy ULg et al

Conference (2012)

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See detailIntegration of InGaAs Channel n-MOS Devices on 200mm Si Wafers Using the Aspect-Ratio-Trapping Technique
Waldron, Niamh; Wang, Gang; Nguyen, Ngoc Duy ULg et al

in 221st ECS Meeting (2012)

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See detailHeterogeneous Integration and Fabrication of III-V MOS Devices in a 200mm Processing Environment
Waldron, Niamh; Nguyen, Ngoc Duy ULg; Lin, Dennis et al

in ECS Transactions (2011), 35

We report on the fabrication of MOS capacitors on 200 mm virtual GaAs substrates using a Si CMOS processing environment. The fabricated capacitors were comparable to those processed on bulk GaAs material ... [more ▼]

We report on the fabrication of MOS capacitors on 200 mm virtual GaAs substrates using a Si CMOS processing environment. The fabricated capacitors were comparable to those processed on bulk GaAs material. Topside contact was made to the GaAs using a novel CMOS compatible self-aligned NiGe contact scheme resulting in a measured contact resistance of 0.26 [ohm sign].cm. Cross-contamination from various III-V substrates was investigated and it was found that by limiting the thermal budget to <= 300C cross-contamination from the outgassing of In, Ga and As could be eliminated. For wet processing the judicious choice of recipe and processing conditions resulted in no significant cross-contamination being detected as determined by TXRF monitoring. This achievement enables III-V device production using state-of-the-art Si processing equipment. [less ▲]

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See detailGrowth of high quality InP layers in STI trenches on miscut Si (001) substrates
Wang, Gang; Leys, Maarten; Nguyen, Ngoc Duy ULg et al

in Journal of Crystal Growth (2011), 315

In this work, we report the selective area epitaxial growth of high quality InP in shallow trench isolation (STI) structures on Si (0 0 1) substrates 6° miscut toward (1 1 1) using a thin Ge buffer layer ... [more ▼]

In this work, we report the selective area epitaxial growth of high quality InP in shallow trench isolation (STI) structures on Si (0 0 1) substrates 6° miscut toward (1 1 1) using a thin Ge buffer layer. We studied the impact of growth rates and steric hindrance effects on the nano-twin formation at the STI side walls. It was found that a too high growth rate induces more nano-twins in the layer and results in InP crystal distortion. The STI side wall tapering angle and the substrate miscut angle induced streric hindrance between the InP facets and the STI side walls also contribute to defect formation. In the [-1 1 0] orientated trenches, when the STI side wall tapering angle is larger than 10°, crystal distortion was observed while the substrate miscut angle has no significant impact on the InP defect formation. In the [-1 1 0] trenches, both the increased STI tapering angle and the substrate miscut angle induce high density of defects. With a small STI tapering angle and a thin Ge layer, we obtained extended defect free InP in the top region of the [1 1 0] trenches with aspect ratio larger than 2. [less ▲]

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See detailN-type and p-type ultra shallow junctions by atomic layer epitaxy and laser anneal
Nguyen, Ngoc Duy ULg; Souriau, Laurent; Shimizu, Yasuo et al

Conference (2011)

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See detailHeterogeneous Integration and Fabrication of III-V MOS Devices in a 200mm Processing Environment
Waldron, Niamh; Nguyen, Ngoc Duy ULg; Lin, Dennis et al

in 219th ECS Meeting (2011)

As CMOS continues to scales to more advanced nodes, new higher mobility channel materials will have to be introduced as an alternative to Si in order to meet power and performance requirements [1]. III-V ... [more ▼]

As CMOS continues to scales to more advanced nodes, new higher mobility channel materials will have to be introduced as an alternative to Si in order to meet power and performance requirements [1]. III-V and Ge materials have emerged as an attractive option for nMOS and pMOS respectively. However, from an economical and technological standpoint it must be possible to implement III-V devices in a Si CMOS fabrication environment to leverage the advantages of both large scale wafers and state-of-the-art Si equipment. The integration challenges of introducing III-V into a Si line include safety risk assessments from toxic materials, maintenance of tools after processing III-V, cross-contamination from high- temperature and wet etch steps, and modifying standard recipes where III-V is exposed on the surface. In this work we demonstrate the feasibility of processing III-V virtual substrates in a Si line following a CMOS based approach that seeks to minimize any potential cross- contamination from the III-V. [less ▲]

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See detailEpitaxial Si, SiGe and Ge for high-performance devices
Loo, Roger; Hikavyy, Andriy; Vincent, Benjamin et al

Conference (2010, September 23)

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See detailSelective Area Growth of InP in Shallow-Trench-Isolated Structures on Off-Axis Si(001) Substrates
Wang, Gang; Leys, Maarten; Nguyen, Ngoc Duy ULg et al

in Journal of the Electrochemical Society (2010), 157(11), 1023

In this paper, we report a comprehensive investigation of InP selective growth in shallow trench isolation (STI) structures on Si(001) substrates 6° off-cut toward (111). Extended defect-free InP layers ... [more ▼]

In this paper, we report a comprehensive investigation of InP selective growth in shallow trench isolation (STI) structures on Si(001) substrates 6° off-cut toward (111). Extended defect-free InP layers were obtained in the top region of 100 nm wide trenches. A thin Ge epitaxial layer was used as an intermediate buffer layer between the Si substrate and the InP layer. A Ge buffer was used to reduce the thermal budget for surface clean and to promote double-step formation on the surfaces. Baking the Ge surface in an As ambient improved the InP surface morphology and crystalline quality. InP showed highly selective growth in trenches without nucleation on SiO2. However, strong loading effects were observed at all growth pressures, which induced variation in local growth rates. We found trench orientation dependence of facet and stacking fault formation. More stacking faults and nanotwins originated from the STI sidewalls in (110) trenches. High quality InP layers were obtained in the top of the trenches along (110). The stacking faults generated by the dissociation of threading dislocations are trapped at the bottom of the trenches with an aspect ratio greater than 2. [less ▲]

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See detailMethod for manufacturing a junction
Nguyen, Ngoc Duy ULg; Loo, Roger; Caymax, Matty

Patent (2010)

The present invention relates to a semiconductor device comprising a homojunction or a heterojunction with a controlled dopant (concentration) profile and a method of making the same. Accordingly, one ... [more ▼]

The present invention relates to a semiconductor device comprising a homojunction or a heterojunction with a controlled dopant (concentration) profile and a method of making the same. Accordingly, one aspect of the invention is a method for manufacturing a junction comprising forming a first semiconductor material comprising a first dopant having a first concentration and thereupon forming a second semiconductor material comprising a second dopant, having a second concentration thereby forming a junction, and depositing by Atomic Layer Epitaxy or Vapor Phase Doping at least a fraction of a monolayer of a precursor suitable to form the second dopant on the first semiconductor material, prior to forming the second semiconductor material, thereby increasing the second concentration of the second dopant at the junction. [less ▲]

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See detailSubstrates and Gate Dielectrics: the Materials Issue for sub-22 nm CMOS Scaling
Caymax, Matty; Bellenger, Florence; Brammertz, Guy et al

Conference (2010, April 08)

Performance scaling of CMOS technologies beyond the 22 nm node will depend on the successful introduction of high mobility materials such as germanium and compound semiconductors on silicon substrates ... [more ▼]

Performance scaling of CMOS technologies beyond the 22 nm node will depend on the successful introduction of high mobility materials such as germanium and compound semiconductors on silicon substrates, which is not straightforward due to important materials incompatibilities. These semiconductors moreover necessitate new gate dielectric materials as the well-proven recipes of “hafnium-based oxides” are not working for various reasons. The lack of a stable, high-quality native oxide for both semiconductors forces materials scientists and device engineers to focus more on the interface rather than on the dielectric material it self. A first part of this paper discusses problems related to the hetero-epitaxial growth of Ge and of III/V materials on Si. By applying a low-high temperature regime, smooth layers of Ge on Si can be obtained. Because of the lattice mismatch, these layers will relax by the formation of misfit dislocations at the interface, combined with threading arms that extend to the surface. The thickness of the layer determines the final density of threading defects, even in case of confined selective growth in windows in a dielectric hard mask, unless specific measures are taken. The polar nature of III/V’s brings about additional problems of anti-phase domain nucleation. This can be solved by providing extra steps on the starting surface in combination with a “pre-deposition” of arsenic. The combination of Ge and III/V selective epitaxy on patterned wafers allows growing confined layers with a low defect density and of high quality. Moreover, by using standard shallow trench isolation as mask, a very natural integration of these materials in standard Si manufacturing can be realized. The second part of this paper deals with the growth of dielectric materials and control of the resulting interfaces. In contrast to the case of Si, both Ge and III/V surfaces are heavily prone to problems with pinning of the surface Fermi level (FLP), which prohibits an efficient control of the channel by varying gate voltages. In the case of Ge, the problem can be solved by decoupling the gate dielectric from the Ge surface by means of an ultra-thin, strained Si epi-layer, after which the well-known gate stack approaches with ALD-grown metal oxides from the Si world can be used. An alternative, promising solution is passivation with thermally grown GeO2 followed by ALD high-k, although this process requires much more care than its Si counterpart. Gate dielectrics on III/V, finally, are probably an even bigger challenge. Apart from the Ga2O+GaGdOx passivation on GaAs, no real solutions of the FLP problem are known. We will discuss the use of sulfur (from thermal treatments with H2S or in the liquid phase with (NH4)2S) in combination with ALD or MBD-grown high-k layers on both GaAs and InGaAs. This will be compared to alternative approaches based on an epitaxially grown interfacial passivation layer of Ge in combination with MBD-grown Al2O3. [less ▲]

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See detailSelective epitaxial growth of III-V semiconductor heterostructures on Si substrates for logic applications
Nguyen, Ngoc Duy ULg; Wang, Gang; Brammertz, Guy et al

in ECS Transactions (2010), 33

We have deposited III-V alloys on 200 mm Si miscut wafers with an oxide pattern. The selective epitaxial growth (SEG) of GaAs in large windows defined by SiO2 lines on a thick strained-relaxed Ge buffer ... [more ▼]

We have deposited III-V alloys on 200 mm Si miscut wafers with an oxide pattern. The selective epitaxial growth (SEG) of GaAs in large windows defined by SiO2 lines on a thick strained-relaxed Ge buffer layer served as a test vehicle which allowed us to demonstrate the integration of a III-V material deposition process step in a Si manufacturing line using an industrial reactor. High quality GaAs layers with high wafer-scale thickness uniformity were achieved. In a subsequent step, SEG of InP was successfully performed on wafers with a 300 nm shallow trench isolation pattern. The seed layer morphology depended on the treatment of the Ge surface and on the growth temperature. The orientation of the trench with respect to the substrate miscut direction had an impact on the quality of the InP filling. Despite of the challenges, such an approach for the integration of III-V materials on Si substrates allowed us to obtain extended-defect-free epitaxial regions suitable for the fabrication of high-performance devices. [less ▲]

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See detailSelective epitaxial growth of InP in STI trenches on off-axis Si(001) substrates
Wang, Gang; Nguyen, Ngoc Duy ULg; Leys, Maarten et al

in ECS Transactions (2010), 27

We report high quality InP layers selectively grown in shallow trench isolation structures on 6 degree offcut Si (001) substrates capped with a thin Ge buffer layer. The Ge layer was used to reduce the ... [more ▼]

We report high quality InP layers selectively grown in shallow trench isolation structures on 6 degree offcut Si (001) substrates capped with a thin Ge buffer layer. The Ge layer was used to reduce the thermal budget for surface clean and double step formation. The atomic steps on the Ge surface were recovered after a bake at 680°C. Smooth nucleation layer was obtained at 420°C on the Ge surface. Baking the Ge surface in As ambient facilitates the InP nulceation and improves the InP crystalline quality. This improvement is attributed to the effective As adsorption on the Ge surface and the polar Ge:As surface prevents the islanding of InP seed layer. Stacking faults were found in the InP layers as a result of threading dislocation dissociation and high quality InP layers were obtained in trenches with aspect ratio greater than 2. [less ▲]

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See detailVapor phase doping for ultra shallow junction formation in advanced Si CMOS devices
Shimizu, Yasuo; Nguyen, Ngoc Duy ULg; Jiang, Sijia et al

Poster (2010)

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See detailIII-V Devices for Advanced CMOS
Waldron, Niamh; Nguyen, Ngoc Duy ULg; Lin, Dennis et al

in 217th ECS Meeting (2010)

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See detailSelective epitaxial growth of III-V semiconductor on large-area Si substrate for advanced logic CMOS technologies
Nguyen, Ngoc Duy ULg; Brammertz, Guy; Wang, Gang et al

Conference (2010)

The continued downscaling of the metal-oxide semiconductor (MOS) transistor for sub-22 nm logic circuits with boosted performance will require the introduction of new channel materials with carrier ... [more ▼]

The continued downscaling of the metal-oxide semiconductor (MOS) transistor for sub-22 nm logic circuits with boosted performance will require the introduction of new channel materials with carrier mobility higher than that of Si, such as Ge for pMOS. The use of III-V compounds for nMOS devices poses however additional challenges related to the hetero-epitaxial growth of a polar semiconductor on a non-polar surface. Furthermore, these high-mobility materials have to be fabricated on large-area Si substrates, in the perspective of application in a standard low-cost very-large-scale integration scheme. In this work, we report on the successful growth of GaAs on 200 mm Si wafers by means of metal-organic vapor deposition using a modified Crius Close-Coupled Showerhead system from AIXTRON AG. We used Si (100) wafers with off-axis orientation (6° miscut towards <111>) in order to avoid the formation of anti-phase domains which lead to Ga-Ga and As-As bonds at their boundaries that have strong detrimental effects on the electrical conduction. In our approach, based on Ge virtual substrates with low threading dislocation (TD) density, the lattice mismatch between Si and GaAs is accommodated and, thus, no additional TD is introduced in the deposited III-V film. Our results show that smooth GaAs layers can be epitaxially grown on large-area Si substrates with high wafer-scale thickness uniformity. The excellent quality of the deposited GaAs was confirmed by photoluminescence and electron microscopy. Our process also demonstrates very high selectivity on patterned wafers with SiO2 mask and enabled the fabrication of capacitor structures using an integration process flow very similar to standard high volume Si manufacturing lines. The capacitance-voltage characteristics were similar to the ones obtained on a bulk GaAs substrate, and showed extremely tight within-wafer and wafer-to-wafer distributions as is standard to Si manufacturing. [less ▲]

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See detailSelective epitaxial growth of III-V semiconductor heterostructures on Si substrates for logic applications
Nguyen, Ngoc Duy ULg; Wang, Gang; Waldron, Niamh et al

in 218th ECS Meeting, 2010 (2010)

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See detailSi/SiGe Resonant Interband Tunneling Diodes Incorporating δ-Doping Layers Grown by Chemical Vapor Deposition
Park, Si-Young; Anisha, Ramesh; Berger, Paul et al

in IEEE Electron Device Letters (2009), 30

This is the first report of a Si/SiGe resonant interband tunneling diodes (RITDs) on silicon substrates grown by the chemical vapor deposition process. The nominal RITD structure forms two quantum wells ... [more ▼]

This is the first report of a Si/SiGe resonant interband tunneling diodes (RITDs) on silicon substrates grown by the chemical vapor deposition process. The nominal RITD structure forms two quantum wells created by sharp delta-doping planes which provide for a resonant tunneling condition through the intrinsic spacer. The vapor phase doping technique was used to achieve abrupt degenerate doping profiles at higher substrate temperatures than previous reports using low-temperature molecular beam epitaxy, and postgrowth annealing experiments are suggestive that fewer point defects are incorporated, as a result. The as-grown RITD samples without postgrowth thermal annealing show negative differential resistance with a recorded peak-to-valley current ratio up to 1.85 with a corresponding peak current density of 0.1 kA/cm2 at room temperature [less ▲]

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See detailSiGe growth using Si3H8 by low temperature chemical vapor deposition
Takeuchi, Shotaro; Nguyen, Ngoc Duy ULg; Goossens, Jozefien et al

in Thin Solid Films (2009), 518(6), 18

Low temperature epitaxial growth of group-IV alloys is a key process step to realize the advanced Si-based devices. In order to keep high growth rate below 600 $\,^ rc$C, trisilane (Si3H8) was used for ... [more ▼]

Low temperature epitaxial growth of group-IV alloys is a key process step to realize the advanced Si-based devices. In order to keep high growth rate below 600 $\,^ rc$C, trisilane (Si3H8) was used for their growth as an alternative Si precursor gas. Then, we compared the use of Si3H8 versus SiH4 for Si1−xGex growth in H2 and N2 as carrier gas by low temperature chemical vapor deposition. By using Si3H8 and controlling GeH4 flow rate, Si1−xGex growth with high growth rate and wide range of Ge concentration has been achieved compared to SiH4-based process. The growth rate and Ge concentration in Si1−xGex with Si3H8 grown at 600 $\,^ rc$C ranged from 11 to 74 nm/min and from 0 to 40%, respectively. The obtained growth rates with Si3H8 are between 1.5 and 6 times higher than for SiH4 at a given growth condition. Si3H8-based in-situ B- and C-doped Si1−xGex growth with high growth rate was also demonstrated [less ▲]

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