  Heterogeneous Integration and Fabrication of III-V MOS Devices in a 200mm Processing Environment; Nguyen, Ngoc Duy  ; et alin ECS Transactions (2011), 35 We report on the fabrication of MOS capacitors on 200 mm virtual GaAs substrates using a Si CMOS processing environment. The fabricated capacitors were comparable to those processed on bulk GaAs material ... [more ▼] We report on the fabrication of MOS capacitors on 200 mm virtual GaAs substrates using a Si CMOS processing environment. The fabricated capacitors were comparable to those processed on bulk GaAs material. Topside contact was made to the GaAs using a novel CMOS compatible self-aligned NiGe contact scheme resulting in a measured contact resistance of 0.26 [ohm sign].cm. Cross-contamination from various III-V substrates was investigated and it was found that by limiting the thermal budget to <= 300C cross-contamination from the outgassing of In, Ga and As could be eliminated. For wet processing the judicious choice of recipe and processing conditions resulted in no significant cross-contamination being detected as determined by TXRF monitoring. This achievement enables III-V device production using state-of-the-art Si processing equipment. [less ▲] Detailed reference viewed: 41 (3 ULg)Heterogeneous Integration and Fabrication of III-V MOS Devices in a 200mm Processing Environment; Nguyen, Ngoc Duy ; et alin 219th ECS Meeting (2011) As CMOS continues to scales to more advanced nodes, new higher mobility channel materials will have to be introduced as an alternative to Si in order to meet power and performance requirements [1]. III-V ... [more ▼] As CMOS continues to scales to more advanced nodes, new higher mobility channel materials will have to be introduced as an alternative to Si in order to meet power and performance requirements [1]. III-V and Ge materials have emerged as an attractive option for nMOS and pMOS respectively. However, from an economical and technological standpoint it must be possible to implement III-V devices in a Si CMOS fabrication environment to leverage the advantages of both large scale wafers and state-of-the-art Si equipment. The integration challenges of introducing III-V into a Si line include safety risk assessments from toxic materials, maintenance of tools after processing III-V, cross-contamination from high- temperature and wet etch steps, and modifying standard recipes where III-V is exposed on the surface. In this work we demonstrate the feasibility of processing III-V virtual substrates in a Si line following a CMOS based approach that seeks to minimize any potential cross- contamination from the III-V. [less ▲] Detailed reference viewed: 95 (3 ULg)Schottky-Barrier height lowering by an increase of the substrate doping in PtSi Schottky barrier source/drain FETsLousberg, Grégory ; ; et alin IEEE Electron Device Letters (2007), 28(2), 123-125 In this letter, the Schottky-barrier height (SBH) lowering in Pt silicide/n-Si junctions and its implications to Schottky-barrier source/drain p-field-effect transistors (p-SBFETs) are studied ... [more ▼] In this letter, the Schottky-barrier height (SBH) lowering in Pt silicide/n-Si junctions and its implications to Schottky-barrier source/drain p-field-effect transistors (p-SBFETs) are studied experimentally and numerically. We demonstrate that the increase of the n-Si substrate doping is responsible for a larger hole SBH lowering through an image-force mechanism, which leads to a substantial gain of the drive current in the long-channel bulk p-SBFETs. Numerical simulations. show that the channel doping concentration is also critical for short-channel p/n-silicon-on-insulator SBFET performance. [less ▲] Detailed reference viewed: 43 (3 ULg)Rapport de la convention d’études pour le suivi scientifique de la réintroduction du saumon atlantique dans le bassin de la Meuse.Philippart, Jean-Claude ; Rimbaud, Gilles ; et alReport (1990) Detailed reference viewed: 7 (2 ULg) |
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