References of "Nguyen, Ngoc Duy"
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See detailA 35nm diameter vertical silicon nanowire short-gate tunnelFET
Vandooren, A.; Rooyackers, R.; Leonelli, D. et al

Conference (2009)

A top-down integration scheme for silicon vertical nanowire (NW) tunnel field-effect transistors (TFETs) with a 35nm nanowire dimension and using state-of-the-art metal gate and high-k gate dielectric is ... [more ▼]

A top-down integration scheme for silicon vertical nanowire (NW) tunnel field-effect transistors (TFETs) with a 35nm nanowire dimension and using state-of-the-art metal gate and high-k gate dielectric is demonstrated. Using the short-gate concept [1], the ambipolar behavior of the TFET is successfully suppressed. The measured TFET performance is not yet beyond that of the MOSFET, most likely due to the use of silicon that has a large bandgap and the use of ion implantation for the formation of the tunnel junction which results in a low junction abruptness. To boost the device performance, a low thermal budget processing could be used on etched nanowires in a substrate with epitaxial grown junction, in order to increase the abruptness of the tunnel junction. [less ▲]

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See detailDepth resolution and surface transients in crystalline Silicon at ultra low energies
Goossens, Jozefien; Berghmans, Bart; Franquet, Alexis et al

Poster (2009)

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See detailVapor phase doping and sub-melt laser anneal for ultra-shallow extension junctions in sub-32 nm CMOS technology
Nguyen, Ngoc Duy ULg; Rosseel, Erik; Takeuchi, Shotaro et al

in Chiussi, S.; Alpuim, P.; Murota, J. (Eds.) et al SiNEP 2009. 1st International Workshop on Si based nano-electronics and -photonics (2009)

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See detailSi$_1-x$Ge$_x$ growth using Si$_3$H$_8$ by low temperature chemical vapor deposition
Takeuchi, Shotaro; Nguyen, Ngoc Duy ULg; Goossens, Jozefien et al

Conference (2009)

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See detail200mm Si/SiGe Resonant Interband Tunneling Diodes Incorporating δ-Doping Layers Grown by CVD
Park, Si-Young; Anisha, Ramesh; Berger, Paul et al

Conference (2009)

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See detailSiGe tunnel field effect transistors: challenges for selective epitaxial growth
Loo, Roger; Iacopi, Francesca; Vanherle, Wendy et al

Conference (2009)

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See detailEnhancement of the poly/mono growth rate ratio for BiCMOS application
Nguyen, Ngoc Duy ULg; Loo, Roger

Report (2008)

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See detailLow-temperature epitaxy of highly-doped n-type Si at high growth rate by chemical vapor deposition for bipolar transistor application
Nguyen, Ngoc Duy ULg; Loo, Roger; Caymax, Matty

in Applied Surface Science (2008), 264

We investigated the growth of in-situ n-type doped epitaxial Si layers with arsenic and phosphorus by means of low-temperature chemical vapor deposition using trisilane as Si-precursor. Indeed, in order ... [more ▼]

We investigated the growth of in-situ n-type doped epitaxial Si layers with arsenic and phosphorus by means of low-temperature chemical vapor deposition using trisilane as Si-precursor. Indeed, in order to prevent the alteration of the characteristics of the devices which are already present on the wafer, an epitaxy process at low temperature is highly desired for applications such as BiCMOS. In this work, the varying parameters are the deposition temperature, the Si-precursor mass flow and the dopant gas flow. As a result, a process for the deposition of heavily doped epilayers was demonstrated at 600 °C with high deposition rate, which is important for maintaining high throughput and low process cost. We showed that using trisilane as a Si-precursor resulted in a much more linear n-type doping behavior than using dichlorosilane. Therefore it allowed an easier process control and a wider dynamic doping range. Our process is an interesting route for the epitaxy of a low-resistance emitter layer for bipolar transistor application. [less ▲]

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See detailVapor phase doping: an atomic layer deposition approach to n-type doping in classical chemical vapor deposition epitaxy
Takeuchi, Shotaro; Nguyen, Ngoc Duy ULg; Leys, Frederik et al

Conference (2008)

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See detailConformal doping of FINFET's : a fabrication and metrology challenge
Vandervorst, Wilfried; Eyben, Pierre; Mody, Jay et al

Conference (2008)

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See detailVapor phase doping with N-type dopant into silicon by atmospheric pressure chemical vapor deposition
Takeuchi, Shotaro; Nguyen, Ngoc Duy ULg; Leys, Frederik et al

in ECS Transactions (2008), 16

Atomic layer doping of phosphorus (P) and arsenic (As) into Si was performed using the vapor phase doping (VPD) technique. For increasing deposition time and precursor gas flow rate, the P and As doses ... [more ▼]

Atomic layer doping of phosphorus (P) and arsenic (As) into Si was performed using the vapor phase doping (VPD) technique. For increasing deposition time and precursor gas flow rate, the P and As doses tend to saturate at about 0.8 and 1.0 monolayer of Si, respectively. Therefore, these processes are self-limited in both cases. When a Si cap layer is grown on the P-covered Si(001), high P concentration of 3.7 × 1020 cm-3 at the heterointerface in the Si- cap/P/Si-substrate layer stacks is achieved. Due to As desorption and segregation toward the Si surface during the temperature ramp up and during the Si-cap growth, the As concentration at the heterointerface in the Si-cap/As/Si-substrate layer stacks was lower compared to the P case. These results allowed us to evaluate the feasibility of the VPD process to fabricate precisely controlled doping profiles. [less ▲]

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See detailStrained silicon on wafer level by wafer bonding: materials processing, strain measurements and strain relaxation
Reiche, M.; Moutanabbir, O.; Himcinschi, C. et al

in ECS Transactions (2008), 16

Different methods to introduce strain in thin silicon device layers are presented. Uniaxial strain is introduced in CMOS devices by process-induced stressors allowing the local generation of tensile or ... [more ▼]

Different methods to introduce strain in thin silicon device layers are presented. Uniaxial strain is introduced in CMOS devices by process-induced stressors allowing the local generation of tensile or compressive strain in the channel region of MOSFETs. Biaxial strain is introduced by growing thin silicon layer on SiGe buffer and transferring it to an oxidized silicon substrates. The latter forms strained silicon on insulator (SSOI) wafer characterized by tensile strain only. Future CMOS device technologies require the combination of the global strain of SSOI substrates with local stressors to increase the device performance. [less ▲]

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See detailImprovement of He ion induced SiGe layer relaxation by a thin Si:C layer
Buca, D.; Trinkaus, H.; Holländer, B. et al

Conference (2008)

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See detailConformal ultra shallow junctions by vapor phase doping with boron
Nguyen, Ngoc Duy ULg; Leys, Frederik; Takeuchi, Shotaro et al

Poster (2008)

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See detailAtomic layer doping of phosphorus and arsenic: experimental and atomistic modeling
Takeuchi, Shotaro; Yang, Lijun; Nguyen, Ngoc Duy ULg et al

Poster (2008)

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See detailVapor phase doping with N-type dopant into silicon by atmospheric pressure chemical vapor deposition
Takeuchi, Shotaro; Nguyen, Ngoc Duy ULg; Leys, Frederik et al

in 214th ECS Meeting, 2008 (2008)

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See detailStrained silicon on wafer level by wafer bonding: materials processing, strain measurements and strain relaxation
Reiche, M.; Moutanabbir, O.; Himcinschi, C. et al

Conference (2008)

Detailed reference viewed: 31 (1 ULg)