References of "Nguyen, Ngoc Duy"
     in
Bookmark and Share    
Full Text
Peer Reviewed
See detailA 400GHz fMAX Fully Self-Aligned SiGe:C HBT Architecture
Van Huylenbroeck, Stefaan; Sibaja-Hernandez, Arturo; Venegas, Rafael et al

in IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2009 (2009)

An improved fully self-aligned SiGe:C HBT architecture featuring a single-step epitaxial collector-base process is described. An fMAX value of 400 GHz is reached by structural as well as intrinsic ... [more ▼]

An improved fully self-aligned SiGe:C HBT architecture featuring a single-step epitaxial collector-base process is described. An fMAX value of 400 GHz is reached by structural as well as intrinsic advancements made to the HBT device. [less ▲]

Detailed reference viewed: 617 (1 ULg)
Full Text
Peer Reviewed
See detailOptimization of external poly base sheet resistance in 0.13 µm quasi self-aligned SiGe:C HBTs
You, Suzhen; Van Huylenbroeck, Stefaan; Nguyen, Ngoc Duy ULg et al

in Thin Solid Films (2009), 518(6), 68

This paper investigates the optimization of the external polysilicon base sheet resistance of quasi self-aligned (QSA) SiGe:C HBTs from a 0.13 μm BiCMOS process. Taking advantage of optimized implant ... [more ▼]

This paper investigates the optimization of the external polysilicon base sheet resistance of quasi self-aligned (QSA) SiGe:C HBTs from a 0.13 μm BiCMOS process. Taking advantage of optimized implant conditions to improve the doping of the external base poly, and using an optimized non-selective epitaxy process with improved growth rate ratio of 1.7 between the polycrystalline silicon and monocrystalline silicon of the base, the maximum oscillation frequency fmax reaches 300 GHz. [less ▲]

Detailed reference viewed: 20 (0 ULg)
Full Text
Peer Reviewed
See detailSi/SiGe Resonant Interband Tunneling Diodes Incorporating δ-Doping Layers Grown by Chemical Vapor Deposition
Park, Si-Young; Anisha, Ramesh; Berger, Paul et al

in IEEE Electron Device Letters (2009), 30

This is the first report of a Si/SiGe resonant interband tunneling diodes (RITDs) on silicon substrates grown by the chemical vapor deposition process. The nominal RITD structure forms two quantum wells ... [more ▼]

This is the first report of a Si/SiGe resonant interband tunneling diodes (RITDs) on silicon substrates grown by the chemical vapor deposition process. The nominal RITD structure forms two quantum wells created by sharp delta-doping planes which provide for a resonant tunneling condition through the intrinsic spacer. The vapor phase doping technique was used to achieve abrupt degenerate doping profiles at higher substrate temperatures than previous reports using low-temperature molecular beam epitaxy, and postgrowth annealing experiments are suggestive that fewer point defects are incorporated, as a result. The as-grown RITD samples without postgrowth thermal annealing show negative differential resistance with a recorded peak-to-valley current ratio up to 1.85 with a corresponding peak current density of 0.1 kA/cm2 at room temperature [less ▲]

Detailed reference viewed: 19 (1 ULg)
Full Text
Peer Reviewed
See detailSiGe growth using Si3H8 by low temperature chemical vapor deposition
Takeuchi, Shotaro; Nguyen, Ngoc Duy ULg; Goossens, Jozefien et al

in Thin Solid Films (2009), 518(6), 18

Low temperature epitaxial growth of group-IV alloys is a key process step to realize the advanced Si-based devices. In order to keep high growth rate below 600 $\,^ rc$C, trisilane (Si3H8) was used for ... [more ▼]

Low temperature epitaxial growth of group-IV alloys is a key process step to realize the advanced Si-based devices. In order to keep high growth rate below 600 $\,^ rc$C, trisilane (Si3H8) was used for their growth as an alternative Si precursor gas. Then, we compared the use of Si3H8 versus SiH4 for Si1−xGex growth in H2 and N2 as carrier gas by low temperature chemical vapor deposition. By using Si3H8 and controlling GeH4 flow rate, Si1−xGex growth with high growth rate and wide range of Ge concentration has been achieved compared to SiH4-based process. The growth rate and Ge concentration in Si1−xGex with Si3H8 grown at 600 $\,^ rc$C ranged from 11 to 74 nm/min and from 0 to 40%, respectively. The obtained growth rates with Si3H8 are between 1.5 and 6 times higher than for SiH4 at a given growth condition. Si3H8-based in-situ B- and C-doped Si1−xGex growth with high growth rate was also demonstrated [less ▲]

Detailed reference viewed: 34 (2 ULg)
Full Text
Peer Reviewed
See detailRelaxation of strained pseudomorphic SixGe1-x layers on He-implanted Si/δ-Si:C/Si(100) substrates
Buca, D.; Minamisawa, R. A.; Trinkaus, H. et al

in Applied Physics Letters (2009), 95

In this letter we present a method to increase the efficiency of SiGe layer relaxation by He+ ion implantation and annealing. Preferential nucleation of He platelets along a 􏰀-impurity layer grown in the ... [more ▼]

In this letter we present a method to increase the efficiency of SiGe layer relaxation by He+ ion implantation and annealing. Preferential nucleation of He platelets along a 􏰀-impurity layer grown in the Si substrate below the SiGe layer results in planar localization and homogenization of dislocation loop sources inducing a more uniform distribution of misfit dislocations. We demonstrate this for a thin Si:C layer grown by reduced pressure chemical vapor deposition. The optimization of the conditions for efficient relaxation and layer quality is studied with respect to the position of the Si:C layer and the process parameters. Relaxation degrees up to 85% are obtained for Si0.77Ge0.23 layers. [less ▲]

Detailed reference viewed: 15 (3 ULg)
Full Text
Peer Reviewed
See detailUse of p- and n-type vapor phase doping and sub-melt laser anneal for extension junctions in sub-32 nm CMOS technology
Nguyen, Ngoc Duy ULg; Rosseel, Erik; Takeuchi, Shotaro et al

in Thin Solid Films (2009), 518(6), 48

We evaluated the combination of vapor phase doping and sub-melt laser anneal as a novel doping strategy for the fabrication of source and drain extension junctions in sub-32 nm CMOS technology, aiming at ... [more ▼]

We evaluated the combination of vapor phase doping and sub-melt laser anneal as a novel doping strategy for the fabrication of source and drain extension junctions in sub-32 nm CMOS technology, aiming at both planar and non-planar device applications. High quality ultra shallow junctions with abrupt profiles in Si substrates were demonstrated on 300 mm Si substrates. The excellent results obtained for the sheet resistance and the junction depth with boron allowed us to fulfill the requirements for the 32 nm as well as for the 22 nm technology nodes in the PMOS case by choosing appropriate laser anneal conditions. For instance, using 3 laser scans at 1300 $\,^ rc$C, we measured an active dopant concentration of about 2.1 × 1020 cm− 3 and a junction depth of 12 nm. With arsenic for NMOS, ultra shallow junctions were achieved as well. However, as also seen for other junction fabrication schemes, low dopant activation level and active dose (in the range of 1--4 × 1013 cm− 2) were observed although dopant concentration versus depth profiles indicate that the dopant atoms were properly driven into the substrate during the anneal step. The electrical deactivation of a large part of the in-diffused dopants was responsible for the high sheet resistance values. [less ▲]

Detailed reference viewed: 56 (4 ULg)
Full Text
Peer Reviewed
See detailZero-Bias Si Backward Diodes Detectors Incorporating P and B δ-Doping Layers Grown by Chemical Vapor Deposition
Park, Si-Young; Anisha, Ramesh; Berger, Paul et al

in International Semiconductor Device Research Symposium, 2009 (2009)

For the first time, CVD-grown Si only backward diode detectors incorporating ¿doping planes were demonstrated. The best performance of curvature coefficient of 16 V-1 with a junction resistance of 14 k¿ ... [more ▼]

For the first time, CVD-grown Si only backward diode detectors incorporating ¿doping planes were demonstrated. The best performance of curvature coefficient of 16 V-1 with a junction resistance of 14 k¿ was shown. By the successful technology transfer from LT-MBE to CVD, the eventual placement of optimized CVD-grown detectors monolithically integrated with 300 mm CMOS platform to fabricate large area focal plane arrays with low cost is now possible. [less ▲]

Detailed reference viewed: 29 (0 ULg)
Full Text
See detailVapor phase doping and sub-melt laser anneal for the fabrication of Si-based ultra-shallow junctions in sub-32 nm CMOS technology
Nguyen, Ngoc Duy ULg; Rosseel, Erik; Takeuchi, Shotaro et al

in International Semiconductor Device Research Symposium, 2009 (2009)

The authors demonstrated that the combination of VPD and LA enables the fabrication of high quality, defect-free USJs with abrupt dopant profile. The results for PMOS with B-VPD are very promising for the ... [more ▼]

The authors demonstrated that the combination of VPD and LA enables the fabrication of high quality, defect-free USJs with abrupt dopant profile. The results for PMOS with B-VPD are very promising for the 32 nm and the 22 nm technology nodes. In the case of NMOS, As-VPD and LA enable the fabrication of an USJ but the electrical deactivation of a large part of the in-diffused dopants is responsible for the high sheet resistance values. [less ▲]

Detailed reference viewed: 30 (3 ULg)
Full Text
See detailA 35nm diameter vertical silicon nanowire short-gate tunnelFET
Vandooren, A.; Rooyackers, R.; Leonelli, D. et al

Conference (2009)

A top-down integration scheme for silicon vertical nanowire (NW) tunnel field-effect transistors (TFETs) with a 35nm nanowire dimension and using state-of-the-art metal gate and high-k gate dielectric is ... [more ▼]

A top-down integration scheme for silicon vertical nanowire (NW) tunnel field-effect transistors (TFETs) with a 35nm nanowire dimension and using state-of-the-art metal gate and high-k gate dielectric is demonstrated. Using the short-gate concept [1], the ambipolar behavior of the TFET is successfully suppressed. The measured TFET performance is not yet beyond that of the MOSFET, most likely due to the use of silicon that has a large bandgap and the use of ion implantation for the formation of the tunnel junction which results in a low junction abruptness. To boost the device performance, a low thermal budget processing could be used on etched nanowires in a substrate with epitaxial grown junction, in order to increase the abruptness of the tunnel junction. [less ▲]

Detailed reference viewed: 158 (3 ULg)
Peer Reviewed
See detailDepth resolution and surface transients in crystalline Silicon at ultra low energies
Goossens, Jozefien; Berghmans, Bart; Franquet, Alexis et al

Poster (2009)

Detailed reference viewed: 25 (0 ULg)
Full Text
Peer Reviewed
See detailVapor phase doping and sub-melt laser anneal for ultra-shallow extension junctions in sub-32 nm CMOS technology
Nguyen, Ngoc Duy ULg; Rosseel, Erik; Takeuchi, Shotaro et al

in Chiussi, S.; Alpuim, P.; Murota, J. (Eds.) et al SiNEP 2009. 1st International Workshop on Si based nano-electronics and -photonics (2009)

Detailed reference viewed: 15 (0 ULg)
Peer Reviewed
See detailSi$_1-x$Ge$_x$ growth using Si$_3$H$_8$ by low temperature chemical vapor deposition
Takeuchi, Shotaro; Nguyen, Ngoc Duy ULg; Goossens, Jozefien et al

Conference (2009)

Detailed reference viewed: 7 (2 ULg)
Full Text
Peer Reviewed
See detail200mm Si/SiGe Resonant Interband Tunneling Diodes Incorporating δ-Doping Layers Grown by CVD
Park, Si-Young; Anisha, Ramesh; Berger, Paul et al

Conference (2009)

Detailed reference viewed: 15 (1 ULg)
Peer Reviewed
See detailSiGe tunnel field effect transistors: challenges for selective epitaxial growth
Loo, Roger; Iacopi, Francesca; Vanherle, Wendy et al

Conference (2009)

Detailed reference viewed: 24 (2 ULg)
See detailEnhancement of the poly/mono growth rate ratio for BiCMOS application
Nguyen, Ngoc Duy ULg; Loo, Roger

Report (2008)

Detailed reference viewed: 8 (0 ULg)
Full Text
Peer Reviewed
See detailLow-temperature epitaxy of highly-doped n-type Si at high growth rate by chemical vapor deposition for bipolar transistor application
Nguyen, Ngoc Duy ULg; Loo, Roger; Caymax, Matty

in Applied Surface Science (2008), 264

We investigated the growth of in-situ n-type doped epitaxial Si layers with arsenic and phosphorus by means of low-temperature chemical vapor deposition using trisilane as Si-precursor. Indeed, in order ... [more ▼]

We investigated the growth of in-situ n-type doped epitaxial Si layers with arsenic and phosphorus by means of low-temperature chemical vapor deposition using trisilane as Si-precursor. Indeed, in order to prevent the alteration of the characteristics of the devices which are already present on the wafer, an epitaxy process at low temperature is highly desired for applications such as BiCMOS. In this work, the varying parameters are the deposition temperature, the Si-precursor mass flow and the dopant gas flow. As a result, a process for the deposition of heavily doped epilayers was demonstrated at 600 °C with high deposition rate, which is important for maintaining high throughput and low process cost. We showed that using trisilane as a Si-precursor resulted in a much more linear n-type doping behavior than using dichlorosilane. Therefore it allowed an easier process control and a wider dynamic doping range. Our process is an interesting route for the epitaxy of a low-resistance emitter layer for bipolar transistor application. [less ▲]

Detailed reference viewed: 32 (3 ULg)
Full Text
Peer Reviewed
See detailVapor phase doping: an atomic layer deposition approach to n-type doping in classical chemical vapor deposition epitaxy
Takeuchi, Shotaro; Nguyen, Ngoc Duy ULg; Leys, Frederik et al

Conference (2008)

Detailed reference viewed: 14 (1 ULg)