References of "Nguyen, Ngoc Duy"
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See detailGrowth of III/V materials on large area silicon
Schineller, Bernd; Nguyen, Ngoc Duy ULg; Heuken, Michael

in ECS Transactions (2010), 28

Continuous miniaturization has been at the heart of advances in modern semiconductor electronics. However, further scalability has seen its limits for conventional CMOS technology due to short channel ... [more ▼]

Continuous miniaturization has been at the heart of advances in modern semiconductor electronics. However, further scalability has seen its limits for conventional CMOS technology due to short channel effects. To further increase the performance for the 32 and 22 nm nodes, channel engineering introducing III-V materials may be necessary. Hence, epitaxial growth and processing strategies have to be developed which combine the high complexity of an MOCVD growth chamber with the requirements of the silicon industry. [less ▲]

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See detailSelective epitaxial growth of InP in STI trenches on off-axis Si(001) substrates
Wang, Gang; Nguyen, Ngoc Duy ULg; Leys, Maarten et al

in ECS Transactions (2010), 27

We report high quality InP layers selectively grown in shallow trench isolation structures on 6 degree offcut Si (001) substrates capped with a thin Ge buffer layer. The Ge layer was used to reduce the ... [more ▼]

We report high quality InP layers selectively grown in shallow trench isolation structures on 6 degree offcut Si (001) substrates capped with a thin Ge buffer layer. The Ge layer was used to reduce the thermal budget for surface clean and double step formation. The atomic steps on the Ge surface were recovered after a bake at 680°C. Smooth nucleation layer was obtained at 420°C on the Ge surface. Baking the Ge surface in As ambient facilitates the InP nulceation and improves the InP crystalline quality. This improvement is attributed to the effective As adsorption on the Ge surface and the polar Ge:As surface prevents the islanding of InP seed layer. Stacking faults were found in the InP layers as a result of threading dislocation dissociation and high quality InP layers were obtained in trenches with aspect ratio greater than 2. [less ▲]

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See detailNon-destructive extraction of junction depths of active doping profiles from photomodulated optical reflectance offset curves
Bogdanowicz, Janusz; Dortu, Fabian; Clarysse, Trudo et al

in Journal of Vacuum Science & Technology : Part B (2010), 28(1), 11

The ITRS Roadmap highlights the electrical characterization of the source and drain extension regions as a key challenge for future complimentary-metal-oxide-semiconductor technology. Presently, an ... [more ▼]

The ITRS Roadmap highlights the electrical characterization of the source and drain extension regions as a key challenge for future complimentary-metal-oxide-semiconductor technology. Presently, an accurate determination of the depth of ultrashallow junctions can routinely only be performed by time-consuming and destructive techniques such as secondary ion mass spectrometry (SIMS). In this work, the authors propose to use the fast and nondestructive photomodulated optical reflectance (PMOR) technique , as implemented in the Therma-Probe\textregistered (TP) dopant metrology system, for these purposes. PMOR is a pump-probe technique based on the measurement of the pump-induced modulated change in probe reflectance, i.e., the so-called (photo) modulated reflectance. In this article, the authors demonstrate that the absolute junction depths of boxlike active dopant structures can be extracted in a very simple and straightforward way from the TP offset curves, which represent the behavior of the modulated reflectance as a function of the pump-probe beam spacing. Although the procedure is based on the insights into the physical behavior of the offset curves, no modeling is involved in the actual extraction process itself. The extracted junction depths are in good correlation with the corresponding junction depths as measured by means of SIMS. The technique has a subnanometer depth sensitivity for depths ranging from 10 to 35 nm with the present Therma-Probe\textregistered 630XP system. The extension of the proposed procedure to the general ultrashallow profiles is also explored and discussed [less ▲]

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See detailVapor phase doping for ultra shallow junction formation in advanced Si CMOS devices
Shimizu, Yasuo; Nguyen, Ngoc Duy ULg; Jiang, Sijia et al

Poster (2010)

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See detailIII-V Devices for Advanced CMOS
Waldron, Niamh; Nguyen, Ngoc Duy ULg; Lin, Dennis et al

in 217th ECS Meeting (2010)

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See detailSelective epitaxial growth of III-V semiconductor on large-area Si substrate for advanced logic CMOS technologies
Nguyen, Ngoc Duy ULg; Brammertz, Guy; Wang, Gang et al

Conference (2010)

The continued downscaling of the metal-oxide semiconductor (MOS) transistor for sub-22 nm logic circuits with boosted performance will require the introduction of new channel materials with carrier ... [more ▼]

The continued downscaling of the metal-oxide semiconductor (MOS) transistor for sub-22 nm logic circuits with boosted performance will require the introduction of new channel materials with carrier mobility higher than that of Si, such as Ge for pMOS. The use of III-V compounds for nMOS devices poses however additional challenges related to the hetero-epitaxial growth of a polar semiconductor on a non-polar surface. Furthermore, these high-mobility materials have to be fabricated on large-area Si substrates, in the perspective of application in a standard low-cost very-large-scale integration scheme. In this work, we report on the successful growth of GaAs on 200 mm Si wafers by means of metal-organic vapor deposition using a modified Crius Close-Coupled Showerhead system from AIXTRON AG. We used Si (100) wafers with off-axis orientation (6° miscut towards <111>) in order to avoid the formation of anti-phase domains which lead to Ga-Ga and As-As bonds at their boundaries that have strong detrimental effects on the electrical conduction. In our approach, based on Ge virtual substrates with low threading dislocation (TD) density, the lattice mismatch between Si and GaAs is accommodated and, thus, no additional TD is introduced in the deposited III-V film. Our results show that smooth GaAs layers can be epitaxially grown on large-area Si substrates with high wafer-scale thickness uniformity. The excellent quality of the deposited GaAs was confirmed by photoluminescence and electron microscopy. Our process also demonstrates very high selectivity on patterned wafers with SiO2 mask and enabled the fabrication of capacitor structures using an integration process flow very similar to standard high volume Si manufacturing lines. The capacitance-voltage characteristics were similar to the ones obtained on a bulk GaAs substrate, and showed extremely tight within-wafer and wafer-to-wafer distributions as is standard to Si manufacturing. [less ▲]

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See detailSelective epitaxial growth of III-V semiconductor heterostructures on Si substrates for logic applications
Nguyen, Ngoc Duy ULg; Wang, Gang; Waldron, Niamh et al

in 218th ECS Meeting, 2010 (2010)

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See detailA 400GHz fMAX Fully Self-Aligned SiGe:C HBT Architecture
Van Huylenbroeck, Stefaan; Sibaja-Hernandez, Arturo; Venegas, Rafael et al

in IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2009 (2009)

An improved fully self-aligned SiGe:C HBT architecture featuring a single-step epitaxial collector-base process is described. An fMAX value of 400 GHz is reached by structural as well as intrinsic ... [more ▼]

An improved fully self-aligned SiGe:C HBT architecture featuring a single-step epitaxial collector-base process is described. An fMAX value of 400 GHz is reached by structural as well as intrinsic advancements made to the HBT device. [less ▲]

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See detailOptimization of external poly base sheet resistance in 0.13 µm quasi self-aligned SiGe:C HBTs
You, Suzhen; Van Huylenbroeck, Stefaan; Nguyen, Ngoc Duy ULg et al

in Thin Solid Films (2009), 518(6), 68

This paper investigates the optimization of the external polysilicon base sheet resistance of quasi self-aligned (QSA) SiGe:C HBTs from a 0.13 μm BiCMOS process. Taking advantage of optimized implant ... [more ▼]

This paper investigates the optimization of the external polysilicon base sheet resistance of quasi self-aligned (QSA) SiGe:C HBTs from a 0.13 μm BiCMOS process. Taking advantage of optimized implant conditions to improve the doping of the external base poly, and using an optimized non-selective epitaxy process with improved growth rate ratio of 1.7 between the polycrystalline silicon and monocrystalline silicon of the base, the maximum oscillation frequency fmax reaches 300 GHz. [less ▲]

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See detailSi/SiGe Resonant Interband Tunneling Diodes Incorporating δ-Doping Layers Grown by Chemical Vapor Deposition
Park, Si-Young; Anisha, Ramesh; Berger, Paul et al

in IEEE Electron Device Letters (2009), 30

This is the first report of a Si/SiGe resonant interband tunneling diodes (RITDs) on silicon substrates grown by the chemical vapor deposition process. The nominal RITD structure forms two quantum wells ... [more ▼]

This is the first report of a Si/SiGe resonant interband tunneling diodes (RITDs) on silicon substrates grown by the chemical vapor deposition process. The nominal RITD structure forms two quantum wells created by sharp delta-doping planes which provide for a resonant tunneling condition through the intrinsic spacer. The vapor phase doping technique was used to achieve abrupt degenerate doping profiles at higher substrate temperatures than previous reports using low-temperature molecular beam epitaxy, and postgrowth annealing experiments are suggestive that fewer point defects are incorporated, as a result. The as-grown RITD samples without postgrowth thermal annealing show negative differential resistance with a recorded peak-to-valley current ratio up to 1.85 with a corresponding peak current density of 0.1 kA/cm2 at room temperature [less ▲]

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See detailSiGe growth using Si3H8 by low temperature chemical vapor deposition
Takeuchi, Shotaro; Nguyen, Ngoc Duy ULg; Goossens, Jozefien et al

in Thin Solid Films (2009), 518(6), 18

Low temperature epitaxial growth of group-IV alloys is a key process step to realize the advanced Si-based devices. In order to keep high growth rate below 600 $\,^ rc$C, trisilane (Si3H8) was used for ... [more ▼]

Low temperature epitaxial growth of group-IV alloys is a key process step to realize the advanced Si-based devices. In order to keep high growth rate below 600 $\,^ rc$C, trisilane (Si3H8) was used for their growth as an alternative Si precursor gas. Then, we compared the use of Si3H8 versus SiH4 for Si1−xGex growth in H2 and N2 as carrier gas by low temperature chemical vapor deposition. By using Si3H8 and controlling GeH4 flow rate, Si1−xGex growth with high growth rate and wide range of Ge concentration has been achieved compared to SiH4-based process. The growth rate and Ge concentration in Si1−xGex with Si3H8 grown at 600 $\,^ rc$C ranged from 11 to 74 nm/min and from 0 to 40%, respectively. The obtained growth rates with Si3H8 are between 1.5 and 6 times higher than for SiH4 at a given growth condition. Si3H8-based in-situ B- and C-doped Si1−xGex growth with high growth rate was also demonstrated [less ▲]

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See detailRelaxation of strained pseudomorphic SixGe1-x layers on He-implanted Si/δ-Si:C/Si(100) substrates
Buca, D.; Minamisawa, R. A.; Trinkaus, H. et al

in Applied Physics Letters (2009), 95

In this letter we present a method to increase the efficiency of SiGe layer relaxation by He+ ion implantation and annealing. Preferential nucleation of He platelets along a 􏰀-impurity layer grown in the ... [more ▼]

In this letter we present a method to increase the efficiency of SiGe layer relaxation by He+ ion implantation and annealing. Preferential nucleation of He platelets along a 􏰀-impurity layer grown in the Si substrate below the SiGe layer results in planar localization and homogenization of dislocation loop sources inducing a more uniform distribution of misfit dislocations. We demonstrate this for a thin Si:C layer grown by reduced pressure chemical vapor deposition. The optimization of the conditions for efficient relaxation and layer quality is studied with respect to the position of the Si:C layer and the process parameters. Relaxation degrees up to 85% are obtained for Si0.77Ge0.23 layers. [less ▲]

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See detailUse of p- and n-type vapor phase doping and sub-melt laser anneal for extension junctions in sub-32 nm CMOS technology
Nguyen, Ngoc Duy ULg; Rosseel, Erik; Takeuchi, Shotaro et al

in Thin Solid Films (2009), 518(6), 48

We evaluated the combination of vapor phase doping and sub-melt laser anneal as a novel doping strategy for the fabrication of source and drain extension junctions in sub-32 nm CMOS technology, aiming at ... [more ▼]

We evaluated the combination of vapor phase doping and sub-melt laser anneal as a novel doping strategy for the fabrication of source and drain extension junctions in sub-32 nm CMOS technology, aiming at both planar and non-planar device applications. High quality ultra shallow junctions with abrupt profiles in Si substrates were demonstrated on 300 mm Si substrates. The excellent results obtained for the sheet resistance and the junction depth with boron allowed us to fulfill the requirements for the 32 nm as well as for the 22 nm technology nodes in the PMOS case by choosing appropriate laser anneal conditions. For instance, using 3 laser scans at 1300 $\,^ rc$C, we measured an active dopant concentration of about 2.1 × 1020 cm− 3 and a junction depth of 12 nm. With arsenic for NMOS, ultra shallow junctions were achieved as well. However, as also seen for other junction fabrication schemes, low dopant activation level and active dose (in the range of 1--4 × 1013 cm− 2) were observed although dopant concentration versus depth profiles indicate that the dopant atoms were properly driven into the substrate during the anneal step. The electrical deactivation of a large part of the in-diffused dopants was responsible for the high sheet resistance values. [less ▲]

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See detailZero-Bias Si Backward Diodes Detectors Incorporating P and B δ-Doping Layers Grown by Chemical Vapor Deposition
Park, Si-Young; Anisha, Ramesh; Berger, Paul et al

in International Semiconductor Device Research Symposium, 2009 (2009)

For the first time, CVD-grown Si only backward diode detectors incorporating ¿doping planes were demonstrated. The best performance of curvature coefficient of 16 V-1 with a junction resistance of 14 k¿ ... [more ▼]

For the first time, CVD-grown Si only backward diode detectors incorporating ¿doping planes were demonstrated. The best performance of curvature coefficient of 16 V-1 with a junction resistance of 14 k¿ was shown. By the successful technology transfer from LT-MBE to CVD, the eventual placement of optimized CVD-grown detectors monolithically integrated with 300 mm CMOS platform to fabricate large area focal plane arrays with low cost is now possible. [less ▲]

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See detailVapor phase doping and sub-melt laser anneal for the fabrication of Si-based ultra-shallow junctions in sub-32 nm CMOS technology
Nguyen, Ngoc Duy ULg; Rosseel, Erik; Takeuchi, Shotaro et al

in International Semiconductor Device Research Symposium, 2009 (2009)

The authors demonstrated that the combination of VPD and LA enables the fabrication of high quality, defect-free USJs with abrupt dopant profile. The results for PMOS with B-VPD are very promising for the ... [more ▼]

The authors demonstrated that the combination of VPD and LA enables the fabrication of high quality, defect-free USJs with abrupt dopant profile. The results for PMOS with B-VPD are very promising for the 32 nm and the 22 nm technology nodes. In the case of NMOS, As-VPD and LA enable the fabrication of an USJ but the electrical deactivation of a large part of the in-diffused dopants is responsible for the high sheet resistance values. [less ▲]

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See detailA 35nm diameter vertical silicon nanowire short-gate tunnelFET
Vandooren, A.; Rooyackers, R.; Leonelli, D. et al

Conference (2009)

A top-down integration scheme for silicon vertical nanowire (NW) tunnel field-effect transistors (TFETs) with a 35nm nanowire dimension and using state-of-the-art metal gate and high-k gate dielectric is ... [more ▼]

A top-down integration scheme for silicon vertical nanowire (NW) tunnel field-effect transistors (TFETs) with a 35nm nanowire dimension and using state-of-the-art metal gate and high-k gate dielectric is demonstrated. Using the short-gate concept [1], the ambipolar behavior of the TFET is successfully suppressed. The measured TFET performance is not yet beyond that of the MOSFET, most likely due to the use of silicon that has a large bandgap and the use of ion implantation for the formation of the tunnel junction which results in a low junction abruptness. To boost the device performance, a low thermal budget processing could be used on etched nanowires in a substrate with epitaxial grown junction, in order to increase the abruptness of the tunnel junction. [less ▲]

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See detailDepth resolution and surface transients in crystalline Silicon at ultra low energies
Goossens, Jozefien; Berghmans, Bart; Franquet, Alexis et al

Poster (2009)

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See detailVapor phase doping and sub-melt laser anneal for ultra-shallow extension junctions in sub-32 nm CMOS technology
Nguyen, Ngoc Duy ULg; Rosseel, Erik; Takeuchi, Shotaro et al

in Chiussi, S.; Alpuim, P.; Murota, J. (Eds.) et al SiNEP 2009. 1st International Workshop on Si based nano-electronics and -photonics (2009)

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