References of "Nguyen, Ngoc Duy"
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See detailProceedings of the 7th International Conference on Si Epitaxy and Heterostructures (ICSI-7)
Hartmann, Jean-Michel; Loo, Roger; Nguyen, Ngoc Duy ULg et al

Book published by Elsevier (2012)

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See detailNumerical simulation of P-OLEDs
Nguyen, Ngoc Duy ULg

Report (2012)

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See detailIntegration of InGaAs Channel n-MOS Devices on 200mm Si Wafers Using the Aspect-Ratio-Trapping Technique
Waldron, Niamh; Wang, Gang; Nguyen, Ngoc Duy ULg et al

in ECS Transactions (2012), 45

We report on the fabrication on InGaAs/InP implant free quantum well (IFQW) n-MOSFET devices on 200mm wafers in a Si CMOS processing environment. The starting virtual InP substrates were prepared by means ... [more ▼]

We report on the fabrication on InGaAs/InP implant free quantum well (IFQW) n-MOSFET devices on 200mm wafers in a Si CMOS processing environment. The starting virtual InP substrates were prepared by means of the aspect-ratio-trapping technique. Post CMP these substrate resulted in a planar substrate with a rms roughness of 0.32 nm. After channel and gate processing source drain regions were formed by the selective epitaxial growth of Si doped InGaAs. Contact to the source/drain regions was made by a standard W-plug/metal 1 process. The contact resistance was estimated to be on the order of 7x10-7 [ohm sign].cm2. Fully processed devices clearly showed gate modulation albeit on top of high levels of source to drain leakage. The source of this leakage was determined to be the result of the unintentional background doping of the InP buffer layer. Simulations show that the inclusion of the p-InAlAs between the InP and InGaAs can effectively suppress this leakage. This work is a significant step towards the integration of InGaAs based devices on a standard CMOS platform. [less ▲]

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See detailIntegration of III-V on Si for High-Mobility CMOS
Waldron, Niamh; Wang, Gang; Nguyen, Ngoc Duy ULg et al

Conference (2012)

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See detailImpedance spectroscopy of GeSn/Ge heterostructures by a numerical method
Baert, Bruno ULg; Nakatsuka, Osamu; Zaima, Shigeaki et al

in 222nd ECS Meeting, 2012 (2012)

In this work, we investigated the electrical characteristics of p-GeSn/p-Ge and p-GeSn/n-Ge structures obtained by simulation of the semiconductor equations. We developed a numerical formalism based on a ... [more ▼]

In this work, we investigated the electrical characteristics of p-GeSn/p-Ge and p-GeSn/n-Ge structures obtained by simulation of the semiconductor equations. We developed a numerical formalism based on a drift-diffusion model including a trap level and applied it to typical GeSn-based heterostructures by focusing on the electrical response under small-signal alternating current regime. The results demonstrate that our method provides an access to both microscopic and macroscopic properties, and thereon, to a physical interpretation of the electrical characteristics of GeSn-based structures by linking measurable quantities to micro-scale variations in the structures. [less ▲]

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See detailArsenic-doped Ge-spiked monoemitter SiGe:C heterojunction bipolar transistors by low-temperature trisilane-based chemical vapor deposition
You, Shuzhen; Decoutere, Stefaan; Nguyen, Ngoc Duy ULg et al

in Thin Solid Films (2012), 520

In this work we optimized the Ge-spiked monoemitter for the SiGe:C heterojunction bipolar transistor by using low-temperature trisilane based chemical vapor deposition to meet the requirements of high ... [more ▼]

In this work we optimized the Ge-spiked monoemitter for the SiGe:C heterojunction bipolar transistor by using low-temperature trisilane based chemical vapor deposition to meet the requirements of high growth rate and high electrically-active doping levels of arsenic. The resultant devices show improvement of open-base breakdown voltage and no degradation of cutoff frequency with incorporation of a Ge spike in the monoemitter. [less ▲]

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See detailIntegration of InGaAs Channel n-MOS Devices on 200mm Si Wafers Using the Aspect-Ratio-Trapping Technique
Waldron, Niamh; Wang, Gang; Nguyen, Ngoc Duy ULg et al

in 221st ECS Meeting (2012)

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See detailHeterogeneous Integration and Fabrication of III-V MOS Devices in a 200mm Processing Environment
Waldron, Niamh; Nguyen, Ngoc Duy ULg; Lin, Dennis et al

in ECS Transactions (2011), 35

We report on the fabrication of MOS capacitors on 200 mm virtual GaAs substrates using a Si CMOS processing environment. The fabricated capacitors were comparable to those processed on bulk GaAs material ... [more ▼]

We report on the fabrication of MOS capacitors on 200 mm virtual GaAs substrates using a Si CMOS processing environment. The fabricated capacitors were comparable to those processed on bulk GaAs material. Topside contact was made to the GaAs using a novel CMOS compatible self-aligned NiGe contact scheme resulting in a measured contact resistance of 0.26 [ohm sign].cm. Cross-contamination from various III-V substrates was investigated and it was found that by limiting the thermal budget to <= 300C cross-contamination from the outgassing of In, Ga and As could be eliminated. For wet processing the judicious choice of recipe and processing conditions resulted in no significant cross-contamination being detected as determined by TXRF monitoring. This achievement enables III-V device production using state-of-the-art Si processing equipment. [less ▲]

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See detailAdmittance spectroscopy study of NiGe contact on GeSn
Truong, Dao Y Nhi ULg; Vertruyen, Bénédicte ULg; Nguyen, Ngoc Duy ULg

Conference (2011)

The direct gap semiconductor germanium tin (GeSn) is an attractive material for next-generation devices in nanoelectronics as well as in photovoltaic applications. However, its detailed electronic ... [more ▼]

The direct gap semiconductor germanium tin (GeSn) is an attractive material for next-generation devices in nanoelectronics as well as in photovoltaic applications. However, its detailed electronic properties have not yet been clearly understood. Recently, admittance spectroscopy has become a popular analytical tool in materials research and development because it involves a relatively simple electrical measurement whose results may establish accurate characteristics of materials. The aim of this work is to study the effects of the annealing temperature on the electrical nature (rectifying or non-rectifying) of the metal contact by admittance spectroscopy. A numerical method, which is based on the solution of the basic semiconductor equations, is applied to simulate the material structure. From the calculation of microscopic quantities such as the modulated carrier concentrations and current densites, we can compute the theoretical admittance and impedance curves as function of frequency and external parameters (temperature and steady-state voltage) and then extract information on the electrical properties of the heterostructure. By a detailed investigation of the impact of microscopic parameters such as the dopant concentrations and the metal barrier height on the electrical characteristics, our objective is to understand the mechanisms of charge transport between the two electrodes. [less ▲]

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See detailNew method for photovoltaic solar cell physical parameters extraction
Aazou, Safae ULg; Ibral, A.; Assaid, M. et al

Conference (2011)

Photovoltaic energy is one of the most important renewable energies. This type of energy, unlike other energy sources, is clean, safe, and abundant. The photovoltaic solar energy is based on the ... [more ▼]

Photovoltaic energy is one of the most important renewable energies. This type of energy, unlike other energy sources, is clean, safe, and abundant. The photovoltaic solar energy is based on the conversion of sunlight into direct current by solar cells. In order to increase the efficiency of the photovoltaic conversion and for a better understanding of the solar cell behavior, an accurate knowledge of the cell physical parameters is required. In this work, the solar cell is considered as a generator and the one-diode equivalent circuit is retained. This electronic circuit modeling the solar cell contains a diode with its reverse saturation current and its ideality factor, parasitic series and shunt resistances and a photocurrent generator. In this paper, a new physical parameters extraction method is presented, for the first time to our knowledge, which is based on the current-voltage characteristics and on the analytical expression of the output voltage given in term of the Lambert W function. This method gives all the physical parameters without any approximation or introduction of initial values. To test the efficiency of the presented method, a comparative study with other extraction methods is done. The obtained results are in good agreement. [less ▲]

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See detailGrowth of high quality InP layers in STI trenches on miscut Si (001) substrates
Wang, Gang; Leys, Maarten; Nguyen, Ngoc Duy ULg et al

in Journal of Crystal Growth (2011), 315

In this work, we report the selective area epitaxial growth of high quality InP in shallow trench isolation (STI) structures on Si (0 0 1) substrates 6° miscut toward (1 1 1) using a thin Ge buffer layer ... [more ▼]

In this work, we report the selective area epitaxial growth of high quality InP in shallow trench isolation (STI) structures on Si (0 0 1) substrates 6° miscut toward (1 1 1) using a thin Ge buffer layer. We studied the impact of growth rates and steric hindrance effects on the nano-twin formation at the STI side walls. It was found that a too high growth rate induces more nano-twins in the layer and results in InP crystal distortion. The STI side wall tapering angle and the substrate miscut angle induced streric hindrance between the InP facets and the STI side walls also contribute to defect formation. In the [-1 1 0] orientated trenches, when the STI side wall tapering angle is larger than 10°, crystal distortion was observed while the substrate miscut angle has no significant impact on the InP defect formation. In the [-1 1 0] trenches, both the increased STI tapering angle and the substrate miscut angle induce high density of defects. With a small STI tapering angle and a thin Ge layer, we obtained extended defect free InP in the top region of the [1 1 0] trenches with aspect ratio larger than 2. [less ▲]

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See detailArsenic-doped Ge-spiked monoemitter SiGe:C HBTs by means of low-temperature trisilane based epitaxy
You, Shuzhen; Decoutere, Stefaan; Nguyen, Ngoc Duy ULg et al

Conference (2011)

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See detailN-type and p-type ultra shallow junctions by atomic layer epitaxy and laser anneal
Nguyen, Ngoc Duy ULg; Souriau, Laurent; Shimizu, Yasuo et al

Conference (2011)

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See detailHeterogeneous Integration and Fabrication of III-V MOS Devices in a 200mm Processing Environment
Waldron, Niamh; Nguyen, Ngoc Duy ULg; Lin, Dennis et al

in 219th ECS Meeting (2011)

As CMOS continues to scales to more advanced nodes, new higher mobility channel materials will have to be introduced as an alternative to Si in order to meet power and performance requirements [1]. III-V ... [more ▼]

As CMOS continues to scales to more advanced nodes, new higher mobility channel materials will have to be introduced as an alternative to Si in order to meet power and performance requirements [1]. III-V and Ge materials have emerged as an attractive option for nMOS and pMOS respectively. However, from an economical and technological standpoint it must be possible to implement III-V devices in a Si CMOS fabrication environment to leverage the advantages of both large scale wafers and state-of-the-art Si equipment. The integration challenges of introducing III-V into a Si line include safety risk assessments from toxic materials, maintenance of tools after processing III-V, cross-contamination from high- temperature and wet etch steps, and modifying standard recipes where III-V is exposed on the surface. In this work we demonstrate the feasibility of processing III-V virtual substrates in a Si line following a CMOS based approach that seeks to minimize any potential cross- contamination from the III-V. [less ▲]

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See detailElectrical characterization of semiconductor heterostructures by admittance spectroscopy
Nguyen, Ngoc Duy ULg

Scientific conference (2010, December 16)

Electrical characterization by admittance spectroscopy enables the study of interface properties of semiconductor structures such as p-n junctions, Schottky diodes, light-emitting systems, photodiodes ... [more ▼]

Electrical characterization by admittance spectroscopy enables the study of interface properties of semiconductor structures such as p-n junctions, Schottky diodes, light-emitting systems, photodiodes, solar cells or quantum well devices. The technique consists in monitoring the complex admittance of the device under test as a function of frequency, applied dc voltage and temperature. This method gives a direct access to the emission-capture processes occurring between an impurity level and the conduction or the valence band and leads to the determination of important electronic properties including the activation energy and the carrier capture cross sections. In the case of organic semiconductors, the field-dependent carrier mobility can be measured as well. However, the interpretation of the admittance curves is straightforward only under restrictive assumptions such as full ionization of the shallow dopant, with a concentration larger than the deep impurity concentration. Numerical simulations, based on the solution of the basic semiconductor equations, allow to carry out a detailed analysis of the steady-state and small-signal electrical characteristics of the systems and thus contribute to a better understanding of the conduction mechanisms and of the microscopic origin of the features in the experimental admittance spectra. In this presentation, the results obtained for different structures are shown in order to illustrate the method. [less ▲]

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See detailEpitaxial Si, SiGe and Ge for high-performance devices
Loo, Roger; Hikavyy, Andriy; Vincent, Benjamin et al

Conference (2010, September 23)

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See detailSelective Area Growth of InP in Shallow-Trench-Isolated Structures on Off-Axis Si(001) Substrates
Wang, Gang; Leys, Maarten; Nguyen, Ngoc Duy ULg et al

in Journal of the Electrochemical Society (2010), 157(11), 1023

In this paper, we report a comprehensive investigation of InP selective growth in shallow trench isolation (STI) structures on Si(001) substrates 6° off-cut toward (111). Extended defect-free InP layers ... [more ▼]

In this paper, we report a comprehensive investigation of InP selective growth in shallow trench isolation (STI) structures on Si(001) substrates 6° off-cut toward (111). Extended defect-free InP layers were obtained in the top region of 100 nm wide trenches. A thin Ge epitaxial layer was used as an intermediate buffer layer between the Si substrate and the InP layer. A Ge buffer was used to reduce the thermal budget for surface clean and to promote double-step formation on the surfaces. Baking the Ge surface in an As ambient improved the InP surface morphology and crystalline quality. InP showed highly selective growth in trenches without nucleation on SiO2. However, strong loading effects were observed at all growth pressures, which induced variation in local growth rates. We found trench orientation dependence of facet and stacking fault formation. More stacking faults and nanotwins originated from the STI sidewalls in (110) trenches. High quality InP layers were obtained in the top of the trenches along (110). The stacking faults generated by the dissociation of threading dislocations are trapped at the bottom of the trenches with an aspect ratio greater than 2. [less ▲]

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See detailMethod for manufacturing a junction
Nguyen, Ngoc Duy ULg; Loo, Roger; Caymax, Matty

Patent (2010)

The present invention relates to a semiconductor device comprising a homojunction or a heterojunction with a controlled dopant (concentration) profile and a method of making the same. Accordingly, one ... [more ▼]

The present invention relates to a semiconductor device comprising a homojunction or a heterojunction with a controlled dopant (concentration) profile and a method of making the same. Accordingly, one aspect of the invention is a method for manufacturing a junction comprising forming a first semiconductor material comprising a first dopant having a first concentration and thereupon forming a second semiconductor material comprising a second dopant, having a second concentration thereby forming a junction, and depositing by Atomic Layer Epitaxy or Vapor Phase Doping at least a fraction of a monolayer of a precursor suitable to form the second dopant on the first semiconductor material, prior to forming the second semiconductor material, thereby increasing the second concentration of the second dopant at the junction. [less ▲]

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See detailSubstrates and Gate Dielectrics: the Materials Issue for sub-22 nm CMOS Scaling
Caymax, Matty; Bellenger, Florence; Brammertz, Guy et al

Conference (2010, April 08)

Performance scaling of CMOS technologies beyond the 22 nm node will depend on the successful introduction of high mobility materials such as germanium and compound semiconductors on silicon substrates ... [more ▼]

Performance scaling of CMOS technologies beyond the 22 nm node will depend on the successful introduction of high mobility materials such as germanium and compound semiconductors on silicon substrates, which is not straightforward due to important materials incompatibilities. These semiconductors moreover necessitate new gate dielectric materials as the well-proven recipes of “hafnium-based oxides” are not working for various reasons. The lack of a stable, high-quality native oxide for both semiconductors forces materials scientists and device engineers to focus more on the interface rather than on the dielectric material it self. A first part of this paper discusses problems related to the hetero-epitaxial growth of Ge and of III/V materials on Si. By applying a low-high temperature regime, smooth layers of Ge on Si can be obtained. Because of the lattice mismatch, these layers will relax by the formation of misfit dislocations at the interface, combined with threading arms that extend to the surface. The thickness of the layer determines the final density of threading defects, even in case of confined selective growth in windows in a dielectric hard mask, unless specific measures are taken. The polar nature of III/V’s brings about additional problems of anti-phase domain nucleation. This can be solved by providing extra steps on the starting surface in combination with a “pre-deposition” of arsenic. The combination of Ge and III/V selective epitaxy on patterned wafers allows growing confined layers with a low defect density and of high quality. Moreover, by using standard shallow trench isolation as mask, a very natural integration of these materials in standard Si manufacturing can be realized. The second part of this paper deals with the growth of dielectric materials and control of the resulting interfaces. In contrast to the case of Si, both Ge and III/V surfaces are heavily prone to problems with pinning of the surface Fermi level (FLP), which prohibits an efficient control of the channel by varying gate voltages. In the case of Ge, the problem can be solved by decoupling the gate dielectric from the Ge surface by means of an ultra-thin, strained Si epi-layer, after which the well-known gate stack approaches with ALD-grown metal oxides from the Si world can be used. An alternative, promising solution is passivation with thermally grown GeO2 followed by ALD high-k, although this process requires much more care than its Si counterpart. Gate dielectrics on III/V, finally, are probably an even bigger challenge. Apart from the Ga2O+GaGdOx passivation on GaAs, no real solutions of the FLP problem are known. We will discuss the use of sulfur (from thermal treatments with H2S or in the liquid phase with (NH4)2S) in combination with ALD or MBD-grown high-k layers on both GaAs and InGaAs. This will be compared to alternative approaches based on an epitaxially grown interfacial passivation layer of Ge in combination with MBD-grown Al2O3. [less ▲]

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