References of "Nguyen, Ngoc Duy"
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See detailBandgap Measurement by Spectroscopic Ellipsometry for Strained Ge1-xSnx
Shimura, Yosuke; Wang, Wei; Nieddu, Thomas ULg et al

Conference (2013, June 04)

Detailed reference viewed: 115 (3 ULg)
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See detailComposition and Thickness Dependence of GeSn Growth by Chemical Vapor Deposition
Wang, Wei; Shimura, Yosuke; Nieddu, Thomas ULg et al

Conference (2013, June 04)

Detailed reference viewed: 71 (1 ULg)
Peer Reviewed
See detailStudy of interface trap density in a GeSn MOS structure by numerical simulation of the electrical characteristics
Baert, Bruno ULg; Schmeits, Marcel ULg; Nguyen, Ngoc Duy ULg

Conference (2013, May)

The semiconducting alloy germanium tin (GeSn) is expected to play an important role in the development of high mobility channel materials for next generation CMOS and optoelectronic devices. The two most ... [more ▼]

The semiconducting alloy germanium tin (GeSn) is expected to play an important role in the development of high mobility channel materials for next generation CMOS and optoelectronic devices. The two most interesting features of this material, which is compatible with mainstream Si technology, are its tunable direct band-gap and the possibility to induce strain due to the lattice mismatch with Ge and Si, thereby increasing the holes and electrons mobilities. It has been shown that the interface trap density can be under- or overestimated in Ge-channel MOSFETs when applying conventional measurement techniques such as the conductance method. As this effect is common in low band-gap materials, we expect that it also occurs for GeSn. Following our previous work on metal/GeSn/Ge structures, we have therefore applied our home-built numerical simulation software to a metal/oxide/GeSn MOS structure in order to investigate the result of the presence of such interface states. We discuss possible effects of the interface trap density, interface trap energy and temperature on the electrical characteristics. Successive simulations of both the steady-state and ac small-signal regimes give access to measurable quantities such as the admittance spectrum and the C-V curves. A physical interpretation can be attributed to their variations and an overall comparison can be made with results obtained from equivalent electrical circuit analysis. [less ▲]

Detailed reference viewed: 90 (5 ULg)
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See detailLong term stability of TiO2 templated multilayer films used as high efficiency photoelectrode in liquid DSSCs
Dewalque, Jennifer ULg; Nguyen, Ngoc Duy ULg; Henrist, Catherine ULg et al

Poster (2013, March)

To our knowledge, the stability results reported in the literature only concern cells made from classical doctor-bladed or screen-printed nanoparticles films. This study focuses on the comparison of the ... [more ▼]

To our knowledge, the stability results reported in the literature only concern cells made from classical doctor-bladed or screen-printed nanoparticles films. This study focuses on the comparison of the long-term stability of these cells with DSSCs working with templated mesoporous films. Indeed, the increased surface area of templated films could lead to a faster degradation of the resulting cells. In accordance with IEC:1646:1996 standard tests, light soaking test at 45°C has been applied to determine the cells stability under prolonged illumination. Moreover, thermal stress in the dark has been applied. Unfortunately, due to the sealing material heat resistance, thermal stress test was only performed at 45°C. [less ▲]

Detailed reference viewed: 111 (31 ULg)
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See detailCollection Efficiency and Design Requirements for Metallic Nanowire Networks in Solar Cells
Langley, Daniel ULg; Giusti, Gael; Nguyen, Ngoc Duy ULg et al

Poster (2013)

In using TCMs based on metallic nanowires it is important to determine the effect of nanowire geometry and spatial arrangement on the resulting network. To this end we have extensively simulated the ... [more ▼]

In using TCMs based on metallic nanowires it is important to determine the effect of nanowire geometry and spatial arrangement on the resulting network. To this end we have extensively simulated the effect of wire length and device size on the percolation properties of the network produced. We have performed Monte Carlo simulations of 2D conductive stick networks including for the first time stick lengths approximating nanowires which are produced experimentally. Each simulation is performed based on an average stick length but the actual lengths of the nanowires in the simulation are randomly generated with a normal distribution around the defined average length. The effects of density and length distribution on the percolation threshold are also explored. The results of such simulations are also employed to determine an elementary representative volume, which can be directly applied to a device design by allowing the determination of the nanowire density required to produce a conductive network associated with a characteristic length, such as diffusion length or pixel size. We also extend this work to the specific application of metallic nanowire networks as front electrodes in dye sensitized solar cells (DSSC), allowing a calculation of the collection efficiency as a function of network density. These calculations were based on the diffusion length of electrons generated within a DSSC and a spatial mapping of the collection efficiency function on the solar cell surface. [less ▲]

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See detailImpedance Spectroscopy of GeSn-based Heterostructures
Baert, Bruno ULg; Nakatsuka, Osamu; Zaima, Shigeaki et al

in ECS Transactions (2013), 50(9), 481-490

In this work, we investigated the electrical characteristics of p-GeSn/p-Ge and p-GeSn/n-Ge structures obtained by simulation of the basic semiconductor equations. We developed a numerical formalism based ... [more ▼]

In this work, we investigated the electrical characteristics of p-GeSn/p-Ge and p-GeSn/n-Ge structures obtained by simulation of the basic semiconductor equations. We developed a numerical formalism based on a drift-diffusion model including a trap level and applied it to typical GeSn-based heterostructures by focusing on the electrical response under small-signal alternating current regime. The results demonstrate that our method provides an access to both microscopic and macroscopic properties, and thereon, to a physical interpretation of the electrical characteristics of GeSn-based structures by linking measurable quantities to micro-scale variations in the structures. [less ▲]

Detailed reference viewed: 111 (39 ULg)
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See detailElectrical investigation of TCMs: role of structural defects and external stress
Langley, Daniel ULg; Giusti, Gael; Consonni, Vincent et al

Conference (2012, October 24)

Detailed reference viewed: 19 (5 ULg)
See detailProceedings of the 7th International Conference on Si Epitaxy and Heterostructures (ICSI-7)
Hartmann, Jean-Michel; Loo, Roger; Nguyen, Ngoc Duy ULg et al

Book published by Elsevier (2012)

Detailed reference viewed: 13 (0 ULg)
See detailNumerical simulation of P-OLEDs
Nguyen, Ngoc Duy ULg

Report (2012)

Detailed reference viewed: 25 (0 ULg)
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See detailIntegration of InGaAs Channel n-MOS Devices on 200mm Si Wafers Using the Aspect-Ratio-Trapping Technique
Waldron, Niamh; Wang, Gang; Nguyen, Ngoc Duy ULg et al

in ECS Transactions (2012), 45

We report on the fabrication on InGaAs/InP implant free quantum well (IFQW) n-MOSFET devices on 200mm wafers in a Si CMOS processing environment. The starting virtual InP substrates were prepared by means ... [more ▼]

We report on the fabrication on InGaAs/InP implant free quantum well (IFQW) n-MOSFET devices on 200mm wafers in a Si CMOS processing environment. The starting virtual InP substrates were prepared by means of the aspect-ratio-trapping technique. Post CMP these substrate resulted in a planar substrate with a rms roughness of 0.32 nm. After channel and gate processing source drain regions were formed by the selective epitaxial growth of Si doped InGaAs. Contact to the source/drain regions was made by a standard W-plug/metal 1 process. The contact resistance was estimated to be on the order of 7x10-7 [ohm sign].cm2. Fully processed devices clearly showed gate modulation albeit on top of high levels of source to drain leakage. The source of this leakage was determined to be the result of the unintentional background doping of the InP buffer layer. Simulations show that the inclusion of the p-InAlAs between the InP and InGaAs can effectively suppress this leakage. This work is a significant step towards the integration of InGaAs based devices on a standard CMOS platform. [less ▲]

Detailed reference viewed: 55 (4 ULg)
See detailIntegration of III-V on Si for High-Mobility CMOS
Waldron, Niamh; Wang, Gang; Nguyen, Ngoc Duy ULg et al

Conference (2012)

Detailed reference viewed: 50 (0 ULg)
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See detailImpedance spectroscopy of GeSn/Ge heterostructures by a numerical method
Baert, Bruno ULg; Nakatsuka, Osamu; Zaima, Shigeaki et al

in 222nd ECS Meeting, 2012 (2012)

In this work, we investigated the electrical characteristics of p-GeSn/p-Ge and p-GeSn/n-Ge structures obtained by simulation of the semiconductor equations. We developed a numerical formalism based on a ... [more ▼]

In this work, we investigated the electrical characteristics of p-GeSn/p-Ge and p-GeSn/n-Ge structures obtained by simulation of the semiconductor equations. We developed a numerical formalism based on a drift-diffusion model including a trap level and applied it to typical GeSn-based heterostructures by focusing on the electrical response under small-signal alternating current regime. The results demonstrate that our method provides an access to both microscopic and macroscopic properties, and thereon, to a physical interpretation of the electrical characteristics of GeSn-based structures by linking measurable quantities to micro-scale variations in the structures. [less ▲]

Detailed reference viewed: 52 (8 ULg)
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See detailArsenic-doped Ge-spiked monoemitter SiGe:C heterojunction bipolar transistors by low-temperature trisilane-based chemical vapor deposition
You, Shuzhen; Decoutere, Stefaan; Nguyen, Ngoc Duy ULg et al

in Thin Solid Films (2012), 520

In this work we optimized the Ge-spiked monoemitter for the SiGe:C heterojunction bipolar transistor by using low-temperature trisilane based chemical vapor deposition to meet the requirements of high ... [more ▼]

In this work we optimized the Ge-spiked monoemitter for the SiGe:C heterojunction bipolar transistor by using low-temperature trisilane based chemical vapor deposition to meet the requirements of high growth rate and high electrically-active doping levels of arsenic. The resultant devices show improvement of open-base breakdown voltage and no degradation of cutoff frequency with incorporation of a Ge spike in the monoemitter. [less ▲]

Detailed reference viewed: 33 (3 ULg)
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See detailIntegration of InGaAs Channel n-MOS Devices on 200mm Si Wafers Using the Aspect-Ratio-Trapping Technique
Waldron, Niamh; Wang, Gang; Nguyen, Ngoc Duy ULg et al

in 221st ECS Meeting (2012)

Detailed reference viewed: 43 (3 ULg)
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See detailHeterogeneous Integration and Fabrication of III-V MOS Devices in a 200mm Processing Environment
Waldron, Niamh; Nguyen, Ngoc Duy ULg; Lin, Dennis et al

in ECS Transactions (2011), 35

We report on the fabrication of MOS capacitors on 200 mm virtual GaAs substrates using a Si CMOS processing environment. The fabricated capacitors were comparable to those processed on bulk GaAs material ... [more ▼]

We report on the fabrication of MOS capacitors on 200 mm virtual GaAs substrates using a Si CMOS processing environment. The fabricated capacitors were comparable to those processed on bulk GaAs material. Topside contact was made to the GaAs using a novel CMOS compatible self-aligned NiGe contact scheme resulting in a measured contact resistance of 0.26 [ohm sign].cm. Cross-contamination from various III-V substrates was investigated and it was found that by limiting the thermal budget to <= 300C cross-contamination from the outgassing of In, Ga and As could be eliminated. For wet processing the judicious choice of recipe and processing conditions resulted in no significant cross-contamination being detected as determined by TXRF monitoring. This achievement enables III-V device production using state-of-the-art Si processing equipment. [less ▲]

Detailed reference viewed: 56 (5 ULg)