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See detailIntegration of InGaAs Channel n-MOS Devices on 200mm Si Wafers Using the Aspect-Ratio-Trapping Technique
Waldron, Niamh; Wang, Gang; Nguyen, Ngoc Duy ULg et al

in ECS Transactions (2012), 45

We report on the fabrication on InGaAs/InP implant free quantum well (IFQW) n-MOSFET devices on 200mm wafers in a Si CMOS processing environment. The starting virtual InP substrates were prepared by means ... [more ▼]

We report on the fabrication on InGaAs/InP implant free quantum well (IFQW) n-MOSFET devices on 200mm wafers in a Si CMOS processing environment. The starting virtual InP substrates were prepared by means of the aspect-ratio-trapping technique. Post CMP these substrate resulted in a planar substrate with a rms roughness of 0.32 nm. After channel and gate processing source drain regions were formed by the selective epitaxial growth of Si doped InGaAs. Contact to the source/drain regions was made by a standard W-plug/metal 1 process. The contact resistance was estimated to be on the order of 7x10-7 [ohm sign].cm2. Fully processed devices clearly showed gate modulation albeit on top of high levels of source to drain leakage. The source of this leakage was determined to be the result of the unintentional background doping of the InP buffer layer. Simulations show that the inclusion of the p-InAlAs between the InP and InGaAs can effectively suppress this leakage. This work is a significant step towards the integration of InGaAs based devices on a standard CMOS platform. [less ▲]

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See detailIntegration of III-V on Si for High-Mobility CMOS
Waldron, Niamh; Wang, Gang; Nguyen, Ngoc Duy ULg et al

Conference (2012)

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See detailIntegration of InGaAs Channel n-MOS Devices on 200mm Si Wafers Using the Aspect-Ratio-Trapping Technique
Waldron, Niamh; Wang, Gang; Nguyen, Ngoc Duy ULg et al

in 221st ECS Meeting (2012)

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See detailHeterogeneous Integration and Fabrication of III-V MOS Devices in a 200mm Processing Environment
Waldron, Niamh; Nguyen, Ngoc Duy ULg; Lin, Dennis et al

in 219th ECS Meeting (2011)

As CMOS continues to scales to more advanced nodes, new higher mobility channel materials will have to be introduced as an alternative to Si in order to meet power and performance requirements [1]. III-V ... [more ▼]

As CMOS continues to scales to more advanced nodes, new higher mobility channel materials will have to be introduced as an alternative to Si in order to meet power and performance requirements [1]. III-V and Ge materials have emerged as an attractive option for nMOS and pMOS respectively. However, from an economical and technological standpoint it must be possible to implement III-V devices in a Si CMOS fabrication environment to leverage the advantages of both large scale wafers and state-of-the-art Si equipment. The integration challenges of introducing III-V into a Si line include safety risk assessments from toxic materials, maintenance of tools after processing III-V, cross-contamination from high- temperature and wet etch steps, and modifying standard recipes where III-V is exposed on the surface. In this work we demonstrate the feasibility of processing III-V virtual substrates in a Si line following a CMOS based approach that seeks to minimize any potential cross- contamination from the III-V. [less ▲]

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See detailSelective epitaxial growth of III-V semiconductor heterostructures on Si substrates for logic applications
Nguyen, Ngoc Duy ULg; Wang, Gang; Brammertz, Guy et al

in ECS Transactions (2010), 33

We have deposited III-V alloys on 200 mm Si miscut wafers with an oxide pattern. The selective epitaxial growth (SEG) of GaAs in large windows defined by SiO2 lines on a thick strained-relaxed Ge buffer ... [more ▼]

We have deposited III-V alloys on 200 mm Si miscut wafers with an oxide pattern. The selective epitaxial growth (SEG) of GaAs in large windows defined by SiO2 lines on a thick strained-relaxed Ge buffer layer served as a test vehicle which allowed us to demonstrate the integration of a III-V material deposition process step in a Si manufacturing line using an industrial reactor. High quality GaAs layers with high wafer-scale thickness uniformity were achieved. In a subsequent step, SEG of InP was successfully performed on wafers with a 300 nm shallow trench isolation pattern. The seed layer morphology depended on the treatment of the Ge surface and on the growth temperature. The orientation of the trench with respect to the substrate miscut direction had an impact on the quality of the InP filling. Despite of the challenges, such an approach for the integration of III-V materials on Si substrates allowed us to obtain extended-defect-free epitaxial regions suitable for the fabrication of high-performance devices. [less ▲]

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See detailSelective epitaxial growth of III-V semiconductor heterostructures on Si substrates for logic applications
Nguyen, Ngoc Duy ULg; Wang, Gang; Waldron, Niamh et al

in 218th ECS Meeting, 2010 (2010)

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See detailA 400GHz fMAX Fully Self-Aligned SiGe:C HBT Architecture
Van Huylenbroeck, Stefaan; Sibaja-Hernandez, Arturo; Venegas, Rafael et al

in IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2009 (2009)

An improved fully self-aligned SiGe:C HBT architecture featuring a single-step epitaxial collector-base process is described. An fMAX value of 400 GHz is reached by structural as well as intrinsic ... [more ▼]

An improved fully self-aligned SiGe:C HBT architecture featuring a single-step epitaxial collector-base process is described. An fMAX value of 400 GHz is reached by structural as well as intrinsic advancements made to the HBT device. [less ▲]

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